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| USER'S MANUAL TCC720 32-bit RISC Microprocessor For Digital Media Player Preliminary Rev 0.51 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TABLE OF CONTENTS Preliminary Spec 0.51 TABLE OF CONTENTS 1. INTRODUCTION 1.1 Features 1.2 Pin Description 1.3 Package Diagram 2. ADDRESS & REGISTER MAP 3. DAI (Digital Audio Interface) & CDIF (CD-DSP Interface) 4. INTERRUPT CONTROLLER 5. TIMER / COUNTER 6. GPIO 7. CLOCK GENERATOR 8. USB (Universal Serial Bus) CONTROLLER 9. UART / IrDA 10. GSIO (General Purpose Serial Input/Output) 11. MISCELLANEOUS PERIPHERALS 11.1 ADC 11.2 CODEC 12. DMA CONTROLLER 13. MEMORY CONTROLLER 13.1 Overview 13.2 SDRAM Controller 13.3 Miscellaneous Configuration 13.4 External Memory Controller 13.5 Internal Memories 14. BOOT ROM 14.1 External ROM Boot 14.2 UART Boot 14.3 NAND Boot 14.4 NOR Boot with Security 14.5 HPI Boot 14.6 Development Mode 15. JTAG DEBUG INTERFACE 16. PACKAGE DIMENSION 2 CHAPTER 1 INTRODUCTION TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 1 INTRODUCTION TCC720 is system LSI for digital media player which based on ARM940T, ARM's proprietary 32bit RISC CPU core. It can decode and encode MP3 or other types of audio/voice compression / decompression standards by software based architecture. The on-chip USB controller enables the data transmission between a personal computer and storage of device such as NAND flash, HDD, CD etc, which can be controlled by TCC720. TCC720 also includes on-chip stereo audio CODEC eliminates the need of expensive external audio CODEC. Using I2S port, TCC720 can also use the external audio CODEC by performance or other reason. 1-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 1.1 FEATURES 32bit ARM940TDMI RISC CPU core 8KB instruction/data cache Internal boot ROM of 4Kbytes for various boot procedure(NAND, UART) and security Internal SRAM of 64K bytes for general usage On-chip peripherals Memory controller for various memories such as PROM, FLASH, SRAM, SDRAM IDE Interface for HDD or USB device 4 external interrupts, 9 internal interrupts 4 timer/counters, 2 timers USB1.1 device (Full speed) UART(IrDA) for serial Host I/F GPIO, GSIO I2S interface for internal and external audio CODEC I2S interface for CD-DSP On chip audio CODEC with MIC input General purpose ADC (3 input) 1 Channel DMA for transferring a bulk of data JTAG interface for code debugging 0.25um low power CMOS process 2.5V for core, 3.3V for I/O port 128-pin TQFP Operating up to 120MHz 1.2 APPLICATIONS Portable Digital Audio Encoder/Decoder MP3 Juke Box Digital Audio Encoder/Decoder Digital Internet Radio Server Multimedia Storage Device 1-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 XIN, XOUT, XTIN, XTOUT, XFILT USB_DP / GPIO_B26, USB_DN / GPIO_B27 XA21 / DQM0 XA20 / DQM1 XA[19:18] XA17 / ND_CLE XA16 / ND_ALE / SD_nRAS XA15 / SD_nCAS XA14 / SD_BA1 XA13 / SD_BA0 XA[12:0] XD[15:0] nOE nWE nCS[3:0] / GPIO_B[5:2] SD_nCS / GPIO_B1 SD_CKE / GPIO_B0 SD_CLK ND_nWE / GPIO_B7 IDE_nCS1 / GPIO_B9 CLK Generator Power Manager USB1.1 TCO2 / GPIO_A11 TCO5 / GPIO_A8 TCO1 / GPIO_A7 TCO4 / GPIO_A4 TCO0 / GPIO_A3 TCO3 / GPIO_A0 EXINT3 / GPIO_A15 EXINT2 / GPIO_A14 EXINT1 / GPIO_A13 EXINT0 / GPIO_A12 GSIO2[3:0] / GPIO_A[11:8] GSIO1[3:0] / GPIO_A[7:4] GSIO0[3:0] / GPIO_A[3:0] GPIO_A[15:0] GPIO_B[29:21] GPIO_B[9:7] GPIO_B[5:0] Ext. Memory & IDE Interface ETC logic Timer /// Timer / Timer Timer Timer Timer Counter // Counter Counter Counter Counter Counter Interrupt Controller Boot ROM (512 x 32) SRAM (64K x 8) GSIO GSIO GSIO AHB APB AHB Wrapper GPIO APB Bridge UART/IrDA ARM940T 1 Channel DMA AHB Test Controller TDI TMS TCK nTRST TDO UT_TX / GPIO_B8 UT_RX / GPIO_B9 BCLK / GPIO_B21 LRCK / GPIO_B22 MCLK / GPIO_B23 DAO / GPIO_B24 DAI / GPIO_B25 CDAI / GPIO_A3 CLRCK / GPIO_A2 CBCLK / GPIO_A1 LCH_OUT RCH_OUT RCH_IN MIC_IN LCH_IN DAI (I2S) for CODEC DAI (I2S) for CD-DSP 16bit Audio CODEC 8 Input ADC (8bit) JTAG AHB Arbiter ADIN[7:0] Figure 1.1 Functional Block Diagram 1-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 1.2 Pin Description JTAG Interface Signal Name TDI TMS TCK TDO nTRST NUM 99 100 101 102 103 Type I I I O I Description JTAG serial data input for ARM940T JTAG Test mode select for ARM940T JTAG test clock for ARM940T JTAG serial data output for ARM940T Reset signal for boundary scan logic. Active low. External Memory Interface Signal SD_CKE SD_CLK SD_nCS XA[6:0] XA[12:7] XA[13] XA[14] XA[15] XA[16] XA[17] XA[19:18] XA[21:20] XD[15:9], XD[8:4], XD[3:0] nCS0 / ND_nOE0 nCS1 / ND_nOE1 nCS2 / ND_nOE2 nCS3 / ND_nOE3 IDE_nCS1 ND_nWE nWE nOE READY Shared Signal GPIO_B0 GPO GPIO_B1 SD_BA0 SD_BA1 SD_nCAS ND_ALE, SD_nRAS ND_CLE DQM[0:1] XD[15:9], XD[8:4], XD[3:0] GPIO_B2 GPIO_B3 GPIO_B4 GPIO_B5 GPIO_B9 / UT_RX GPIO_B7 nWE nOE - NUM 56 44 46 23:17 31:26 34 35 36 37 38 40:39 43:42 15:9, 6:2, 128:125 47 48 49 50 61 57 58 59 73 Type O O O O O O O O O O O O I/O O O O O O O O O I SDRAM clock Description Clock enable signal for SDRAM, Active high. / GPIO_B1 Chip select signal for SDRAM, Active low. / GPIO_B0 Address bus for external memories. Bank Address 0 for SDRAM / XA[13] Bank Address 1 for SDRAM / XA[14] CAS for SDRAM / XA[15] ALE for NAND flash / RAS for SDRAM / XA[16] CLE for NAND flash / XA[17] XA[19:18] for static memory / Bus Width configuration XA[21:20] / Data I/O mask Data bus for external memory External chip select 0 / NAND flash 0 OE / GPIO_B2 External chip select 1 / NAND flash 1 OE / GPIO_B3 External chip select 2 / NAND flash 2 OE / GPIO_B4 External chip select 3 / NAND flash 3 OE / GPIO_B5 IDE chip select 1. Active low. / GPIO_B9 / UART RX NAND flash WE. Active low. / GPIO_B7 Static memory write enable signal. Active low. Static memory output enable signal. Active low. Ready information from external device. *) XA[21:0] is used as system address bus for external memories such as SRAM, ROM. XA[12:0] can be also used as RAS and CAS signals for SDRAM. XD[15:0] is used as system data bus for all types of external memories contained. SD_CLK is also used as general purpose output port by setting clock control flag. Refer to the chapter of memory controller for detail. 1-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 General Purpose I/O Signal GPIO_A[15:12] GPIO_A[11:8] Shared Signal EXINT[3:0] GSIO2[3:0] (SDI_2, FRM_2, SCK_2, SDO_2) GSIO1[3:0] NUM 124:121 118:115 114:113 111 108 Type I/O I/O Description GPIO_A[15:12] / External Interrupt Source 3 ~ 0 GPIO_A[11:8] / General Purpose Serial I/O 2 GPIO_A[7:4] (SDI_1, FRM_1, SCK_1, SDO_1) GSIO0[3:1] (SDI_0, FRM_0, SCK_0) / CDIF[2:0] (CDAI, CLRCK, CBCLK) GSIO0[0] (SDO_0) USB_DP, USB_DN DAI DAO I/O GPIO_A[7:4] / General Purpose Serial I/O 1 GPIO_A[3:1] 107:105 I/O GPIO_A[3:1] / General purpose serial I/O 0 / CD interface signals GPIO_A[0] / General purpose serial out 0 GPIO_B[29:28] GPIO_B[27:26] / USB_DP, USB_DN GPIO_A[0] GPIO_B[29:28] GPIO_B[27:26] 104 54:53 52:51 68 67 66 63 62 61 60 57 50:47 46 56 I/O I/O I/O GPIO_B[25:21] MCLK LRCK BCLK UT_RX / IDE_nCS1 UT_TX ND_nWE nCS[3:0] SD_nCS SD_CKE I/O GPIO_B[25:21] / I2S Interface Signals GPIO_B[9:8] GPIO_B7 GPIO_B[5:2] GPIO_B1 GPIO_B0 I/O I/O I/O I/O I/O GPIO_B[9:8] / UART Interface Signals IDE chip select 1 GPIO_B7 / Write enable for NAND flash GPIO_B[5:2] / External Chip Select 3 ~ 0 GPIO_B1 / Chip select for SDRAM GPIO_B0 / SDRAM clock control 1-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 USB / UART / IrDA Interface Signal USB D+ USB DUART_TXD UART_RXD Shared Signal GPIO_B26 GPIO_B27 GPIO_B8 GPIO_B9 / IDE_nCS1 NUM 51 52 60 61 Type I/O I/O I/O I/O Description USB Function D+ pin / GPIO_B26 USB Function D- pin / GPIO_B27 UART or IrDA TX data pin / GPIO_B8 UART or IrDA RX data pin / GPIO_B9 IDE chip select 1 Audio Interface Signal GPIO_B21 GPIO_B22 GPIO_B23 GPIO_B24 GPIO_B25 LCH_IN RCH_IN MIC_IN LCH_OUT RCH_OUT VREF Shared Signal BCLK LRCK MCLK DAO DAI LCH_IN RCH_IN MIC_IN LCH_OUT RCH_OUT VREF NUM 62 63 66 67 68 90 91 92 93 94 95 Type I/O I/O I/O I/O I/O I I I O O O Description I2S Bit clock (64fs) / GPIO_B21 I2S Word clock / GPIO_B22 I2S system clock (256fs or 384fs) / GPIO_B23 I2S digital audio data output / GPIO_B24 I2S digital audio data input / GPIO_B25 ADC left channel input of internal audio CODEC ADC right channel input of internal audio CODEC Mic input of internal audio CODEC DAC left channel output of internal audio CODEC DAC right channel output of internal audio CODEC Reference voltage of internal audio CODEC CD DSP Interface Signal CBCLK CLRCK CDAI Shared Signal GPIO_A1 GPIO_A2 GPIO_A3 NUM 105 106 107 Type I/O I/O I/O Description CD Data Bit Clock Input / GPIO_A1 CD Data Word Clock Input / GPIO_A2 CD Data input / GPIO_A3 Clock Interface Signal XIN XOUT XFILT XTIN XTOUT Shared Signal - NUM 74 75 78 69 70 Type I O O I O Description Main clock input for PLL Main clock output for PLL PLL filter output Sub clock input Sub clock output External Interrupt Interface Signal Shared Signal GPIO_A15 EXINT[3:0] GPIO_A14 GPIO_A13 GPIO_A12 NUM 124 123 122 121 Type Description I/O External interrupt request [3:0] / GPIO_A[15:12] 1-6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 General Purpose ADC Interface Signal ADIN[2:0] Shared Signal - NUM 84:82 Type I Description General purpose multi-channel ADC input Mode Control Signal MODE1 nRESET Shared Signal - NUM 98 72 Type I I System Reset Description Mode Setting Input 1 Power Signal NUM 112 76 64 33 16 119 109 87 71 41 24 7 89 81 77 97 65 45 32 1 120 110 88 55 25 8 96 86 85 80 79 Type Description VDD3 PWR Digital Power for I/O (3.3V) VDD2D PWR Digital Power for Internal (2.5V) VDD2A PWR Analog Power (2.5V) VSS3D PWR Digital Ground for I/O VSS2D PWR Digital Ground for Internal VSSA PWR Analog Ground 1-7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 1.3 Package Diagram MCLK/GPIO_B23 66 DAO/GPIO_B24 67 DAI/GPIO_B25 VDDA_CDC VDDA_ADC VSSA_CDC VBBA_ADC VSSA_ADC VDDA_PLL VBBA_PLL VSSA_PLL RCH_OUT LCH_OUT VDDI_AIP VSSI_AIP nRESET RCH_IN LCH_IN READY MIC_IN XTOUT VDDIO 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 VSSIO MODE1 TDI TMS TCK TDO nTRST SDO0/GPIO_A0 SCK0/GPIO_A1 SFRM0/GPIO_A2 SDI0/GPIO_A3 SDO1/GPIO_A4 VDDI VSSI SCK1/GPIO_A5 VDDIO SFRM1/GPIO_A6 SDI1/GPIO_A7 SDO2/GPIO_A8 SCK2/GPIO_A9 SFRM2/GPIO_A10 SDI2/GPIO_A11 VDDI VSSI EXINT0/GPIO_A12 EXINT1/GPIO_A13 EXINT2/GPIO_A14 EXINT3/GPIO_A15 XD0 XD1 XD2 XD3 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 65 VSSIO ADIN4 ADIN2 ADIN0 XOUT XFILT VREF VDDI XTIN XIN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDIO LRCK/GPIO_B22 BCLK/GPIO_B21 UT_RX/IDE_nCS1/GPIO_B9 UT_TX/GPIO_B8 nOE nWE ND_nWE/GPIO_B7 SD_CKE/GPIO_B0 VSSI GPIO_B29 GPIO_B28 USB_DN/GPIO_B27 USB_DP/GPIO_B26 nCS3/nOE3/GPIO_B5 nCS2/nOE2/GPIO_B4 nCS1/nOE1/GPIO_B3 nCS0/nOE0/GPIO_B2 SD_nCS/GPIO_B1 VSSIO SD_CLK/GPO XA21/DQM0 XA20/DQM1 VDDI XA19 XA18 XA17/CLE XA16/nRAS/ALE XA15/nCAS XA14/BA1 XA13/BA0 VDDIO TCC720 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDI VSSIO VDDI VDDIO Figure 1.2 Package Diagram (128-TQFP-1414) VSSIO VSSI VSSI XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XD4 XD5 XD6 XD7 XD8 XA9 XA10 XA11 XD10 XD11 XD12 XD13 XD14 XD15 XA12 XD9 1-8 CHAPTER 2 ADDRESS & REGISTER MAP TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 2 ADDRESS & REGISTER MAP 2.1 Address Map The TCC720 has fixed address maps for digital audio en-decoder system. The address space is separated MSB 4bits of address bus, the following table represents overall address space of TCC720 system. Table 2.1 Address Allocation Map of TCC720 Address Space Device Name internal or external ROM of chip select 3 (Remap == 0) 0x00000000 ~ 0x0FFFFFFF Other type memory according to base value (Remap = 1) Internal SRAM when any other memory is not assigned. 0x10000000 ~ 0x1FFFFFFF 0x20000000 ~ 0x2FFFFFFF 0x30000000 ~ 0x3FFFFFFF 0x40000000 ~ 0x4FFFFFFF Not Used Initial area for SDRAM Area of internal SRAM Initial area for chip select 0 Initial configuration is for SRAM Initial area for chip select 1 Initial configuration is for IDE type device Initial area for chip select 2 Initial configuration is for NAND flash Initial area for chip select 3 Initial configuration is for ROM Various internal peripheral devices 0x50000000 ~ 0x5FFFFFFF 0x60000000 ~ 0x6FFFFFFF 0x70000000 ~ 0x7FFFFFFF 0x80000000 ~ 0x8FFFFFFF 0x90000000 ~ 0x9FFFFFFF 0xA0000000 ~ 0xAFFFFFFF 0xB0000000 ~ 0xBFFFFFFF 0xC0000000 ~ 0xCFFFFFFF 0xD0000000 ~ 0xDFFFFFFF 0xE0000000 ~ 0xEFFFFFFF 0xF0000000 ~ 0xFFFFFFFF Not Used Area for internal boot ROM Area for memory controller configuration register space The address space (0x00000000 ~ 0x0FFFFFFF) is initially allocated to internal or external PROM for booting procedure, and a special flag is exist in memory controller unit for remapping lower half space to other type memories. Refer to the description of memory controller for 2-1 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 detailed operation. TCC720 has only one chip select for SDRAM, so its address space is dependent on SDRAM size attached to TCC720. TCC720 has various peripherals for controlling a digital audio en-decoder system. These peripherals can be configured appropriately by it's own registers that can be accessed through specially allocated address. These address maps are represented in the following table. In case of memory controller, its space is separated for preventing illegal accessing. Refer to corresponding sections for detail information of each peripheral. Table 2.2 Address Allocation for Internal Peripherals (Base Address = 0x80000000) Offset Address Space 0x000 ~ 0x0FF 0x100 ~ 0x1FF 0x200 ~ 0x2FF 0x300 ~ 0x3FF 0x400 ~ 0x4FF 0x500 ~ 0x5FF 0x600 ~ 0x6FF 0x700 ~ 0x7FF 0x800 ~ 0x8FF 0x900 ~ 0x9FF 0xA00 ~ 0xAFF 0xB00 ~ 0xBFF 0xC00 ~ 0xCFF 0xD00 ~ 0xDFF 0xE00 ~ 0xEFF 0xF00 ~ 0xFFF Peripheral DAI & CDIF Interrupt Controller Timer Counter GPIO Clock Generator & Power Management USB Function UART/IrDA GSIO (General Purpose Serial Input/Output) Analog Control & Etc. DMA Controller - *) Address decoding logic only monitors base address (i.e. 0x8xxxxxxx), and bit11~bit8 of accessing address bus. So care must be taken not to modify these registers unintentionally. 2-2 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 2.2 Register Map DAI & CDIF Register Map (Base Address = 0x80000000) Name DADI_L0 DADI_R0 DADI_L1 DADI_R1 DADO_L0 DADO_R0 DADO_L1 DADO_R1 DAMR DAVC CDDI_0 CDDI_1 CICR Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x80 0x84 0x88 Type R R R R R/W R/W R/W R/W R/W R/W R R R/W Reset 0x0000 0x0000 0x0000 Description Digital Audio Left Input Register 0 Digital Audio Right Input Register 0 Digital Audio Left Input Register 1 Digital Audio Right Input Register 1 Digital Audio Left Output Register 0 Digital Audio Right Output Register 0 Digital Audio Left Output Register 1 Digital Audio Right Output Register 1 Digital Audio Mode Register Digital Audio Volume Control Register CD Digital Audio Input Register 0 CD Digital Audio Input Register 1 CD Interface Control Register Interrupt Controller Register Map (Base Address = 0x80000100) Name IEN CREQ IREQ IRQSEL ICFG MREQ IRQREQ FIQREQ Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Type R/W W R R/W R/W R R R Reset 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Description Interrupt Enable Register Clear Interrupt Request Register Interrupt Request Flag Register IRQ/FIQ Select Register External Interrupt Configuration Register Masked Interrupt Request Flag Register IRQ Interrupt Request Flag Register FIQ Interrupt Request Flag Register 2-3 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Timer/Counter Register Map (Base Address = 0x80000200) Name TCFG0 TCNT0 TREF0 TMREF0 TCFG1 TCNT1 TREF1 TMREF1 TCFG2 TCNT2 TREF2 TMREF2 TCFG3 TCNT3 TREF3 TMREF3 TCFG4 TCNT4 TREF4 TCFG5 TCNT5 TREF5 TIREQ TWDCFG TWDCLR Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x0050 0x0054 0x0058 0x0060 0x0070 0x0074 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Reset 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x00000 0xFFFFF 0x00 0x00000 0xFFFFF 0x0000 0x0000 Description Timer/Counter 0 Configuration Register Timer/Counter 0 Counter Register Timer/Counter 0 Reference Register Timer/Counter 0 Middle Reference Register Timer/Counter 1 Configuration Register Timer/Counter 1 Counter Register Timer/Counter 1 Reference Register Timer/Counter 1 Middle Reference Register Timer/Counter 2 Configuration Register Timer/Counter 2 Counter Register Timer/Counter 2 Reference Register Timer/Counter 2 Middle Reference Register Timer/Counter 3 Configuration Register Timer/Counter 3 Counter Register Timer/Counter 3 Reference Register Timer/Counter 3 Middle Reference Register Timer/Counter 4 Configuration Register Timer/Counter 4 Counter Register Timer/Counter 4 Reference Register Timer/Counter 5 Configuration Register Timer/Counter 5 Counter Register Timer/Counter 5 Reference Register Timer/Counter n Interrupt Request Register Watchdog Timer Configuration Register Watchdog Timer Clear Register 2-4 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO Register Map (Base Address = 0x80000300) Name GDATA_A GIOCON_A GSEL_A GTSEL_A GDATA_B GIOCON_B GSEL_B GTSEL_B Addr 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Type R/W R/W R/W R/W R/W R/W R/W R/W Reset Description 0xFFFFFFFF GPIO_A Data Register 0xFFFF0000 0x00000000 0x00000000 GPIO_A Direction Control Register GPIO_A Function Select Register GPIO_A Function Select Register 2 0x3FFFFFFF GPIO_B Data Register 0x001FFCFF GPIO_B Direction Control Register 0x3C0000BF GPIO_B Function Select Register 0x00000000 GPIO_B Function Select Register 2 Clock Generator Register Map (Base Address = 0x80000400) Name CKCTRL PLLMODE SCLKmode DCLKmode EXTCLKmode UTCLKmode UBCLKmode TCLKmode GCLKmode SW_nRST Address 0x00 0x04 0x08 0x0C 0x14 0x18 0x1C 0x24 0x28 0x3C Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x0003FFE 0x03806 0x082000 0x0800 0x0000 0x01BE 0x000 0x000 0x000 0x000 Description Clock Control Register PLL Control Register System Clock Control Register DCLK (DAI/CODEC) Control Register EXTCLK (CD/Other) Control Register UTCLK (UART) Control Register UBCLK (USB) Control Register TCLK (Timer) Control Register GCLK (GSIO) Control Register Software Reset Control Register 2-5 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB Register Map (Base Address = 0x80000500) Name UBFADR UBPWR UBIIR UBOIR UBIR UBIIEN UBOIEN UBIEN UBFRM1 UBFRM2 UBIDX INMXPn INCSR1n INCSR2n OMXPn OCSR1n OCSR2n OFIFO1n OFIFO2n EP0FIFO EP1FIFO EP2FIFO Address 0x00 0x04 0x08 0x10 0x18 0x1C 0x24 0x2C 0x30 0x34 0x38 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x80 0x84 0x88 Type Reset Description Function Address Register Power Management Register In-Interrupt Register Out-Interrupt Register Interrupt Register In-Interrupt Enable Register Out-Interrupt Enable Register Interrupt Enable Register Frame Number 1 Register Frame Number 2 Register Index Register IN Max Packet Register IN CSR1 Register IN CSR2 Register OUT Max Packet Register OUT CSR1 Register OUT CSR2 Register OUT FIFO Write Count 1 Register OUT FIFO Write Count 2 Register EP0 FIFO Register EP1 FIFO Register EP2 FIFO Register 2-6 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART/IrDA Register Map (Base Address = 0x80000600) Name RB THR DL IR CR LSR IrDACFG1 IrDACFG2 Address 0x00 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Type R W W R/W R/W R R/W R/W Reset 0x0000 0x000 0x000 0x0101 0x0003 0x4da1 Description Receiver Buffer Register Transmitter Holding Register Divisor Latch Register Interrupt Register UART Control Register Status Register IrDA Configuration Register 1 IrDA Configuration Register 2 GSIO Register Map (Base Address = 0x80000700) Name GSDO0 GSDI0 GSCR0 GSICR GSDO1 GSDI1 GSCR1 GSDO2 GSDI2 GSCR2 GSDO3 GSDI3 GSCR3 Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Description GSIO0 Output Data Register GSIO0 Input Data Register GSIO0 Control Register GSIO Interrupt Control Register GSIO1 Output Data Register GSIO1 Input Data Register GSIO1 Control Register GSIO2 Output Data Register GSIO2 Input Data Register GSIO2 Control Register GSIO3 Output Data Register GSIO3 Input Data Register GSIO3 Control Register 2-7 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Analog Interface & ETC Register Map (Base Address = 0x80000A00) Name ADCTR ADDATA CDCTR CDCGAIN LZC USBCTR TSTSEL Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Type R/W R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Description ADC Control Register ADC Data Register Codec Control Register Codec Gain Register Leading Zero Counter Register USB Port Control Register Test Mode Register (must be remained zero) DMA Controller Register Map (Base Address = 0x80000E00) Name ST_SADR SPARAM C_SADR ST_DADR DPARAM C_DADR HCOUNT CHCTRL Address 0x00 0x04/0x08 0x0C 0x10 0x14/0x18 0x1C 0x20 0x24 Type R/W R/W R R/W R/W R R/W R/W Reset Description Start Address of Source Block Parameter of Source Block Current Address of Source Block Start Address of Destination Block Parameter of Destination Block Current Address of Destination Block 0x00000000 Initial and Current Hop count 0x00000000 Channel Configuration Memory Controller Register Map (Base Address = 0xF0000000) Name SDCFG SDFSM MCFG TST CSCFG0 Address 0x00 0x04 0x08 0x0C 0x10 Type R/W R R/W W R/W Reset 0x4268A020 0xZZZZ_02 0x0000 0x0B405601 Description SDRAM Configuration Register SDRAM FSM Status Register Miscellaneous Configuration Register Test mode register (must be remained zero) External Chip Select 0 Configuration Register (Initially set to SRAM) External Chip Select 1 Configuration CSCFG1 0x14 R/W 0x0150569A Register (Initially set to IDE) External Chip Select 2 Configuration CSCFG2 0x18 R/W 0x0060569A Register (Initially set to NAND) External Chip Select 3 Configuration CSCFG3 0x1C R/W 0x0A70569A Register (Initially set to NOR) 2-8 TCC720 ADDRESS & REGISTER MAP Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 NAND flash Register Map (Base Address = N * 0x10000000) Name CMD LADDR BADDR IADDR DATA Address 0x00 0x04 0x08 0x0C 0x10 Type R/W W W W R/W Reset Description Command Cycle Register Linear Address Cycle Register Block Address Cycle Register Single Address Cycle Register Data Access Cycle Register *) N represents BASE field of CSCFGn registers. 2-9 CHAPTER 3 DAI & CDIF TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 3 DAI (Digital Audio Interface) & CDIF (CD-DSP Interface) 3.1 DAI The TCC720 provides digital audio interface that complies with IIS (Inter-IC Sound). The DAI has five input/output pins for IIS interface; MCLK, BCLK, LRCK, DAI, DAO. All DAI input/output pins are multiplexed with GPIO pins; GPIO_B<21:25>. The MCLK is the system clock pin that is used for CODEC system clock. The DAI provides 256fs, 384fs and 512fs as a system clock. 256fs means that 256 times of sampling frequency fs. The BCLK is the serial bit clock for IIS data exchange. The DAI can generate 64fs, 48fs and 32fs by dividing a system clock. The polarity of BCLK can be programmed. The LRCK is the frame clock for the audio channel Left and Right. The frequency of LRCK is the "fs" - sampling frequency. Generally, for audio application - such as MP3 Player , CD player, 11.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz. the fs can be set to 8kHz, 16kHz, For supporting the wide range of sampling frequency in audio application, the DCO function is very useful to generate a system clock. Refer Chap. 7 for detail information. All three clocks are selectable as master or slave. The DAI, DAO are the serial data input output pins respectively. The DAI has two 8-word input/output buffers. The buffers can be read/written through the DADI/DADO. The hidden buffer pointers automatically increment when user read/write from/to the DADI/DADO. The maximum data word size is 24 bit. Data is justified to MSB of 32bits and zeros are padded to LSB. There are 2 types of interrupt from IIS; transmit done interrupt, receive done interrupt. The transmit-done interrupt is generated when the 4 words are transferred successfully in the output buffer. At this interrupt, user should fill another 4 more words into the other part of the output buffer in the interrupt service routine (ISR). In this ISR routine, 4 consecutive stores of word data to the DADO is needed - sequence is that the left channel is the first and right channel. The receive-done interrupt is generated when the 4 words are received successfully in the input buffer. At this interrupt, user should read 4 received words from the input buffer using 4 consecutive load instructions from the DADI - sequence is that the left channel is the first. 3-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 DAI Register Map (Base Address = 0x80000000) Name DADI_L0 DADI_R0 DADI_L1 DADI_R1 DADO_L0 DADO_R0 DADO_L1 DADO_R1 DAMR DAVC Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 Type R R R R R/W R/W R/W R/W R R/W Reset 0x0000 0x0000 Description Digital Audio Left Input Register 0 Digital Audio Right Input Register 0 Digital Audio Left Input Register 1 Digital Audio Right Input Register 1 Digital Audio Left Output Register 0 Digital Audio Right Output Register 0 Digital Audio Left Output Register 1 Digital Audio Right Output Register 1 Digital Audio Mode Register Digital Audio Volume Control Register 3-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 Digital Audio Mode Register (DAMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000020 17 16 Reserved 15 EN 14 TE 13 RE 12 MD 11 SM 10 BM 9 FM 8 CC 7 6 5 4 3 BP 2 1 0 LB BD<1:0> FD<1:0> CM MM EN [15] 0 1 DAI Master Enable DAI disabled DAI enabled TE [14] 0 1 DAI Transmitter Enable DAI transmitter disabled DAI transmitter enabled RE [13] 0 1 DAI Receiver Enable DAI receiver disabled DAI receiver enabled MD [12] 0 1 DAI Bus Mode DAI has IIS bus mode DAI has MSB justified mode SM [11] 0 1 DAI System Clock Master Select DAI system clock is come from external pin DAI system clock is generated by the clock generator block BM [10] 0 1 DAI Bit Clock Master Select DAI bit clock is come from external pin DAI bit clock is generated by dividing DAI system clock FM [9] 0 1 DAI Frame Clock Master Select DAI frame clock is come from external pin DAI frame clock is generated by dividing DAI bit clock 3-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 CC [8] 0 1 CDIF Clock Select CDIF Clock master mode disabled CDIF Clock master mode enabled. BD [7:6] 00 01 10 11 DAI Bit Clock Divider select Div 4 ( 256fs->64fs ) Div 6 ( 384fs->64fs ) Div 8 ( 512fs->64fs, 384fs->48fs , 256fs->32fs) Div16 ( 512fs->32fs ) FD [5:4] 00 01 10 DAI Frame Clock Divider select Div 32 ( 32fs->fs ) Div 48 ( 48fs->fs ) Div 64 ( 64fs->fs ) BP [3] 0 1 DAI Bit Clock Polarity Data is captured at positive edge of bit clock Data is captured at negative edge of bit clock CM [2] 0 1 CDIF Monitor Mode CDIF monitor mode is disabled CDIF monitor mode is enabled. Data bypass from CDIF MM [1] 0 1 DAI Monitor Mode DAI monitor mode is disabled DAI monitor mode is enabled. TE should be enabled LB [0] 0 1 DAI Loop-back Mode DAI Loop back mode is disabled DAI Loop back mode is enabled 3-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 Digital Audio Volume Control Register (DAVC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000024 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VC<3:0> VC [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DAI Volume control 0dB -6dB -12dB -18dB -24dB -30dB -36dB -42dB -48dB -54dB -60dB -66dB -72dB -78dB -84dB -90dB 3-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 Input Buffer DADI Input Buffer Pointer LEFT0 RIGHT0 LEFT1 RIGHT1 LEFT2 RIGHT2 LEFT3 RIGHT3 MM CDIF Data CC IIS_SDO LB DAVC S2P IIS_SDI Output Buffer DADO Output Buffer Pointer LEFT0 RIGHT0 LEFT1 RIGHT1 LEFT2 RIGHT2 LEFT3 RIGHT3 P2S DCO SM IIS_MCLK DIVIDER CDIF BCLK CC BM IIS_BCLK CDIF LRCK DIVIDER CC FM IIS_LRCK Figure 3.1 DAI Block Diagram 3-6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 LRCK 16 15 14 13 12 Left 11 10 9 8 7 6 5 4 3 2 1 Right 16 BCLK DAI/O L S B M S B L S B M S B MD=0 (IIS mode), BP=0, BCLK = 32fs LRCK 32 31 30 29 28 27 Left 10 9 8 7 6 5 4 3 2 1 32 Right BCLK DAI/O M S B L S B M S B MD=1(MSB justified mode), BP=0, BCLK=64fs LRCK 24 23 22 21 20 21 Left 9 8 7 6 5 4 3 2 1 Right BCLK DAI/O M S B L S B M S B MD=1(MSB justified mode), BP=1, BCLK=48fs Figure 3.2 DAI Bus Timing Diagram 3-7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 3.2 CDIF The TCC720 provides CD-ROM interface for feasible implementation of CD-ROM application such as CD-MP3 player. The CDIF supports the industry standard IIS format and the LSB justified format that is used as the most popular format for CD-ROM interface by Sony and Samsung. The CDIF has three pins for interface; CBCLK, CLRCK, CDAI that are multiplexed with GPIO_B14, GPIO_B15 and GPIO_B16, respectively. The CBCLK is the bit clock input pins of which frequency can be programmed by CICR for selection of 48fs and 32fs. The CLRCK is the frame clock input pin that indicates the channel of CD digital audio data. The CDAI is the input data pin. The CDIF has three registers; CDDI_0, CDDI_1 and CICR. The CDDI_0 and the CDDI_1 are the banked read only registers for access of data input buffer. The data input buffer is composed of four 32 bit wide registers of which upper 16 bit is left channel data and lower is right channel data. The CDIF receive the serial data from CDAI pin and store the data into the buffer through the serial to parallel register. Whenever the half of buffer is filled, the receive interrupt is generated. Only the half of input buffer can be accessible through the CDDI_0 and the CDDI_1. CDIF Register Map (Base Address = 0x80000000) Name CDDI_0 CDDI_1 CICR Address 0x80 0x84 0x88 Type R R R/W 0x0000 Reset Description CD Digital Audio Input Register 0 CD Digital Audio Input Register 1 CD Interface Control Register CD Data Input (CDDI0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000080 17 16 Left Channel Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Right Channel Data CD Data Input (CDDI1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000084 17 16 Left Channel Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Right Channel Data 3-8 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 CD Interface Control Register (CICR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000088 17 16 Reserved 15 14 13 12 11 10 9 8 7 EN 6 5 Reserved 4 3 BS 2 1 MD 0 BP Reserved EN [7] 0 1 CDIF Enable CDIF disabled CDIF enabled BS [3:2] 00 01 10 CDIF Bit Clock select 64fs 32fs 48fs MD [1] 0 1 Interface Mode select IIS format LSB justified format BP [3] 0 1 CDIF Bit Clock Polarity Data is captured at positive edge of bit clock Data is captured at negative edge of bit clock 3-9 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DAI & CDIF Preliminary Spec 0.51 Input Buffer CDDI0 CDDI1 LEFT0 RIGHT0 LEFT1 RIGHT1 Input Buffer Pointer LEFT2 RIGHT2 LEFT3 RIGHT3 CBCLK CLRCK S2P CDAI Figure 3.3. CDIF Block Diagram CLRCK 24 23 22 21 20 Left 19 10 9 8 7 6 5 4 3 2 1 Right 16 CBCLK CDAI M S B L S B M S B MD=0 (IIS mode), BP=0, CBCLK=48fs CLRCK 24 23 22 21 20 19 Left 18 17 16 15 6 5 4 3 2 1 Right CBCLK CDAI M S B L S B MD=1(LSB justified mode), BP=0, CBCLK=48fs Figure 3.3 CDIF Bus Timing Diagram 3 - 10 CHAPTER 4 INTERRUPT CONTROLLER TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTERRUPT CONTROLLER Preliminary Spec 0.51 4 INTERRUPT CONTROLLER 4.1 Overview Interrupt controller can manage up to 16 interrupt sources. In TCC720, there are 4 external interrupt sources that can be detected various kind of method, that is a rising edge/ falling edge / level high / level low detection can be set for external interrupt sources. External interrupt sources can be reliably managed with noise filtering up to 100 ~ 400 us. There are two types of interrupt in ARM940T, IRQ type, FIQ type. Interrupt controller can manage these two types for each interrupt sources separately. The following figure represents the block diagram of interrupt controller. pi_INTIN pi_EXTIN Clock Generator Noise Filter Edge/Level Selector ICFG IREQ APB IRQ Flag CREQ MREQ IEN nIRQ/nFIQ Generator IRQSEL nFIQ nIRQ Figure 4.1 Interrupt Controller Block Diagram 4-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTERRUPT CONTROLLER Preliminary Spec 0.51 4.2 Register Description Interrupt Controller Register Map (Base Address = 0x80000100) Name IEN CREQ IREQ IRQSEL ICFG MREQ TSTREQ Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Type R/W W R R/W R/W R R/W Reset 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Description Interrupt Enable Register Clear Interrupt Request Register Interrupt Request Flag Register IRQ/FIQ Select Register External Interrupt Configuration Register Masked Interrupt Request Flag Register Test Mode Register (must be remained zero) Interrupt Enable Register (IEN) 15 MEN 0x80000100 9 GS 14 - 13 12 11 10 - 8 UB 7 UT 6 TC 5 I2T 4 I2R 3 E3 2 E2 1 E1 0 E0 DMA LCD CDIF MEN [15] 0 1 All interrupts are disabled Master Enable All interrupt enabled by corresponding bit[14:0] can be passed to CPU Bit Field Each Interrupt Request Control 1 = Interrupt enabled, 0 = Interrupt disabled DMA [13] LCD [12] CDIF [11] [10] GS [9] UB [8] UT [7] TC [6] I2T [5] I2R [4] E3 [3] E2 [2] DMA interrupt control LCD interrupt control CDIF interrupt control Not used GSIO interrupt control USB interrupt control UART/IrDA interrupt control Timer/Counter interrupt control I2S TX interrupt control I2S RX interrupt control External interrupt request 3 control External interrupt request 2 control 4-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTERRUPT CONTROLLER Preliminary Spec 0.51 E1 [1] E0 [0] External interrupt request 1 control External interrupt request 0 control Clear Interrupt Request Register (CREQ) 15 - 0x80000104 8 7 UT 14 - 13 12 11 10 - 9 GS 6 TC 5 I2T 4 I2R 3 E3 2 E2 1 E1 0 E0 DMA LCD CDIF UB *) When writing "1" to each field, the interrupt request flag of corresponding interrupt is cleared. Interrupt Request Register (IREQ) 15 - 0x80000108 9 GS 14 - 13 12 11 10 - 8 UB 7 UT 6 TC 5 I2T 4 I2R 3 E3 2 E2 1 E1 0 E0 DMA LCD CDIF *) When each field is "1", the corresponding interrupt has been requested and not cleared. IRQ Interrupt Select Register (IRQSEL) 15 - 0x8000010C 8 UB 14 - 13 12 11 10 - 9 GS 7 UT 6 TC 5 I2T 4 I2R 3 E3 2 E2 1 E1 0 E0 DMA LCD CDIF *) When each field is "1", the corresponding interrupt is considered as IRQ interrupt, otherwise as FIQ interrupt. External Interrupt Configuration Register (ICFG) 15 FE3 0x80000110 6 5 4 FT1 14 13 12 FT3 11 FE2 10 9 8 FT2 7 FE1 3 FE0 2 1 0 FT0 DTYPE3 DTYPE2 DTYPE1 DTYPE0 FE3~FE0 0 1 Filter Enable Noise filter is enabled (in case of DTYPEn != 3) Noise filter is disabled (in case of DTYPEn != 3) *) If DTYPEn == 3, noise filter is always enabled, and this field sets which level generates the interrupt. If it is set to 1, level high triggers interrupt, and if it is set to 0, level low triggers interrupt. DTYPE3~0 0 1 2 3 Detection Type Falling edge triggered external interrupt Rising edge triggered external interrupt Both edge triggered external interrupt Level high / low triggered external interrupt FEn field determines which level triggers the interrupt. If FEn == 1, level high triggers the interrupt and FEn == 0, level low triggers the interrupt. 4-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTERRUPT CONTROLLER Preliminary Spec 0.51 FT3~FT0 0 Filter Type Clock based filter is used. The filter delay is proportional to PCLK period as the following equations. Filter Delay = TPCLK * 64 If PCLK has 25MHz, then the filter delay has about 16us. 1 Delay cell based filter is used. The filter delay varies on the operating conditions, like voltage, temperature, etc. The nominal delay is about 120ns. This type of filter must be selected when the PCLK has to be stopped, as like as stop mode etc. Masked Interrupt Request Register (MREQ) 15 - 0x80000114 7 UT 14 - 13 12 11 10 - 9 GS 8 UB 6 TC 5 I2T 4 I2R 3 E3 2 E2 1 E1 0 E0 DMA LCD CDIF *) Same meaning as IREQ except that it represents only the enabled interrupt's request. 4-4 CHAPTER 5 TIMER / COUNTER TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TIMER / COUNTER Preliminary Spec 0.51 5 TIMER / COUNTER 5.1 Overview The TCC720 has four 16bit and two 20bit timer counter. Each timer counter has 3 registers for various operation modes. Refer to register description table for details. When operating in counter modes, External interrupt pin is used as counting clock for that counter. The main clock frequency of timer counter can be configured by setting TCLK frequency. (Refer to Clock generator block) With the 12bit internal basic counter, the timer counter can generate various intervals from micro-seconds to seconds unit. The following figure represents the block diagram of timer counter. pi_EXTIN Basic Counter Clock Selector Counter TCFG APB TCNT TREF Compare (=) TREQ Tgl TCO Figure 5.1 Timer Counter Block Diagram The following table explains the three registers of each timer counter. The address of each timer counter is 16bytes aligned. The base address of timer counter is 0x80000200. The number n represents for each timer/counter. In case of timer/counter 4, 5 (that is n = 4 or 5) 5-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TIMER / COUNTER Preliminary Spec 0.51 the TREF, TCNT register has 20bit resolution. It can be used for generation of a long time period. 5.2 Register Description Timer/Counter Register Map (Base Address = 0x80000200) Name TCFG0 TCNT0 TREF0 TMREF0 TCFG1 TCNT1 TREF1 TMREF1 TCFG2 TCNT2 TREF2 TMREF2 TCFG3 TCNT3 TREF3 TMREF3 TCFG4 TCNT4 TREF4 TCFG5 TCNT5 TREF5 TIREQ TWDCFG TWDCLR Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x0050 0x0054 0x0058 0x0060 0x0070 0x0074 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Reset 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x00000 0xFFFFF 0x00 0x00000 0xFFFFF 0x0000 0x0000 Description Timer/Counter 0 Configuration Register Timer/Counter 0 Counter Register Timer/Counter 0 Reference Register Timer/Counter 0 Middle Reference Register Timer/Counter 1 Configuration Register Timer/Counter 1 Counter Register Timer/Counter 1 Reference Register Timer/Counter 1 Middle Reference Register Timer/Counter 2 Configuration Register Timer/Counter 2 Counter Register Timer/Counter 2 Reference Register Timer/Counter 2 Middle Reference Register Timer/Counter 3 Configuration Register Timer/Counter 3 Counter Register Timer/Counter 3 Reference Register Timer/Counter 3 Middle Reference Register Timer/Counter 4 Configuration Register Timer/Counter 4 Counter Register Timer/Counter 4 Reference Register Timer/Counter 5 Configuration Register Timer/Counter 5 Counter Register Timer/Counter 5 Reference Register Timer/Counter n Interrupt Request Register Watchdog Timer Configuration Register Watchdog Timer Clear Register 5-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TIMER / COUNTER Preliminary Spec 0.51 Timer/Counter n Configuration Register (TCFGn) 15 14 13 12 0 0x800002n0 6 5 TCKSEL 11 10 9 8 CC 7 POL 4 3 2 1 0 EN IEN PWM CON CC [8] 0 1 TCNTn hold its value. TCNTn is cleared to zero. Clear Count POL [7] 0 1 TCK Polarity TCNTn is incremented at rising edge of the selected counting clock TCNTn is incremented at falling edge of the selected counting clock TCKSEL [6:4] k=0~4 k = 5, 6 k=7 TCK Select TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 2(k+1). TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 22k TCK is the external pin shared by external interrupt signal. In TCC721, there are 4 external pins for this purpose, so this configuration is valid only for timer/counter 3 ~ 0. (not for timer/counter 5, 4) IEN [3] 1 Interrupt Enable Timer/Counter interrupt is enabled PWM [2] 1 PWM Mode Enable Timer/Counter Output is changed at every time the TCNTn is equal to TREFn and TMREFn value. It can be used to generate PWM waveform, by changing TMREFn while fixing TREFn. (where, TREFn > TMREFn) CON [1] 0 1 Continue Counting TCNTn is stop counting at the time TCNTn is equal to TREFn When the TCNTn is reached to TREFn, TCNTn continues counting from 0 at the next pulse of selected clock source EN [0] 1 Timer/Counter Enable Timer counter is enabled. TCNTn value is cleared at the same time. 5-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TIMER / COUNTER Preliminary Spec 0.51 Timer/Counter n Counting Register (TCNTn) 31 30 29 28 27 26 0 0x800002n4 23 22 21 20 19 18 17 16 25 24 TCNTn[19:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCNTn[15:0] *) TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to any value by writing the value to this register. In case of timer 4 and timer 5, it has 20bit. Timer/Counter n Counting Reference Register (TREFn) 31 30 29 28 27 26 0 0x800002n8 21 20 19 18 17 16 25 24 23 22 TREFn[19:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TREFn[15:0] *) When TCNTn is reached at TREFn, the TCNTn is cleared to 0. According to the TCFGn settings, various kinds of operations may be done. In case of timer 4 and timer 5, it has 20bit. 5-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TIMER / COUNTER Preliminary Spec 0.51 Timer/Counter Interrupt Request Register (TIREQ) 15 0 0x80000260 6 TW 14 13 12 TF4 11 TF3 10 TF2 9 TF1 8 TF0 7 0 5 TI5 4 TI4 3 TI3 2 TI2 1 TI1 0 TI0 TWF TF5 TWF 1 Watchdog Timer Flag Watchdog timer has reached to its reference value. TFn 1 TWI 1 Timer/Counter n Flag Timer/counter n has been overflowed. Watchdog Timer Interrupt Request Flag Watchdog timer has generated its interrupt. TIn 1 Timer/Counter n Interrupt Request Flag Timer/counter n has generated its interrupt. *) if a timer n has reached its reference value, the TFn is set. (bit n represents for Timer n). If its interrupt request is enabled by set bit 3 of TCFGn register, the TIn is set. And if the TC bit of IEN register is set, the timer interrupt is really generated, and this TIREQ register is used to determine which timer has requested the interrupt. After checking these flags, user can clear these TFn, TIn field by writing "1" to corresponding TIn bit field. 5-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 TIMER / COUNTER Preliminary Spec 0.51 Watchdog Timer Configuration Register (TWDCFG) 15 14 13 12 0 0x80000270 6 5 TCKSEL 11 10 9 8 7 0 4 3 IEN 2 0 1 RST 0 EN Watchdog timer is used for the system not to be stuck by generating a reset pulse automatically when the watchdog timer counter overflows to zero. The programmer must clear the watchdog counter before it overflows by writing any value to TWDCLR register. TCKSEL [6:4] k=0~4 TCK Select TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 2(k+1). k = 5, 6 TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 22k k=7 Undefined. Should not be used. IEN [3] 1 Interrupt Enable Watchdog Timer Interrupt is initiated. This field is valid only if RST field is set to 0. RST [1] 0 Reset Enable Watchdog timer does not generate reset signal although it reaches to the reference value, and it continue counting from 0. 1 Watchdog timer generates the reset signal when it reaches to the reference value, the reset signal is applied to every component in the chip. EN [0] 1 Watchdog Timer Enable Watchdog timer is enabled. If the watchdog timer is disabled, its counter goes to 0xffe0, so when it is first enabled, user must clear the counter by writing to TWDCLR register. Watchdog Timer Clear Register (TWDCLR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000274 1 0 any value *) The watchdog timer counter can be cleared to 0 by writing any value to this register. If it is not cleared before it overflows, the watchdog timer generate reset signal to the entire component of chip. 5-6 CHAPTER 6 GPIO PORT TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 6 GPIO (General Purpose I/O) PORT 6.1 Functional Description The TCC720 has a lot of general purpose I/Os that can be programmed by setting internal registers. All I/Os are set to input mode at reset. The block diagram of GPIO is in the following figure. GIOCON Output of other block Output of test or other block Write APB GDATA 2 MUX 1 0 GPIO pin 1 MUX Read GDATA GSEL, TSEL 0 Figure 6.1 GPIO Block Diagram The I/O mode can be set by the state of GIOCONn register. If a bit of GIOCONn register is 1, the corresponding GPIO pin has come to output mode, and if 0, which is the default state of GIOCON register, the corresponding GPIO pin is set to input mode. If GPIO pin is set to input mode, GPIO pin's state can be fed to CPU by reading GDATAn register and when output mode, GPIO pin's state can be controlled by the state of the corresponding bit of GDATAn register. If GDATAn register is read when the mode is output mode, the value that CPU gets is the one 6-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 that CPU has written before. In TCC720, there are various kinds of peripherals that generate its own control signals. These peripherals can occupy the dedicated GPIO pins. This option is controlled by the state of the GSELx register. If a bit of these GSELx is 1, the corresponding GPIO pin is entered to other function mode, so used by other peripherals not by GPIO block. The direction control method of GPIO pins in the other function mode is determined case by case. One of them follows the normal direction control method using GDDR register, the other method uses a dedicated direction control signals. 6-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 6.2 Register Description GPIO Register Map (Base Address = 0x80000300) Name GDATA_A GIOCON_A GSEL_A GTSEL_A GDATA_B GIOCON_B GSEL_B GTSEL_B Addr 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 0xFFFFFFFF 0x00000000 0x00000000 0x00000000 0x3FFFFFFF 0x001FFCFF 0x3C0000BF 0x00000000 Description GPIO_A Data Register GPIO_A Direction Control Register GPIO_A Function Select Register 1 GPIO_A Function Select Register 2 GPIO_B Data Register GPIO_B Direction Control Register GPIO_B Function Select Register 1 GPIO_B Function Select Register 2 6-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 GPIO_A Data Register (GDATA_A) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000300 17 16 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data for GPIO_A[15:0] pin GPIO_A Direction Control Register (GIOCON_A) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000304 17 16 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direction control for GPIO_A[15:0] pin *) if a bit is set to 1, the corresponding GPIO pin is set to output mode. GPIO_A Function Select Register (GSEL_A) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 9 GS2[2:0] 8 7 6 5 GS1[2:0] 4 3 2 1 GS0[2:0] 0 23 22 21 20 19 18 0x80000308 17 16 *) if a bit is set to 1, the corresponding GPIO pin is used by the other dedicated function blocks. GSn[2:0] 0 GS2[2] = 1 GS2[1] = 1 GS2[0] = 1 GS1[2] = 1 GS1[1] = 1 GS1[0] = 1 GS0[2] = 1 GS0[1] = 1 GS0[0] = 1 GPIO_A[10:8], GPIO_A[6:4], GPIO_A[2:0] Function GPIO_A[10:8], GPIO_A[6:4], GPIO_A[2:0] pin is working as Normal GPIO Function GPIO_A[10] : FRM signal of GSIO2 block GPIO_A[ 9] : SCK signal of GSIO2 block GPIO_A[ 8] : SDO signal of GSIO2 block GPIO_A[ 6] : FRM signal of GSIO1 block GPIO_A[ 5] : SCK signal of GSIO1 block GPIO_A[ 4] : SDO signal of GSIO1 block GPIO_A[ 2] : FRM signal of GSIO0 block GPIO_A[ 1] : SCK signal of GSIO0 block GPIO_A[ 0] : SDO signal of GSIO0 block *) SDI signal for GSIO2, GSIO1, GSIO0 block is always fed through GSIO_A[11], GSIO_A[7], GSIO_A[3] pin regardless of these GS[2:0] bit. But these pins must be set to input mode. 6-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 GPIO_A Test Select Register (GTSEL_A) 31 30 29 28 27 26 25 24 0 15 14 0 13 12 11 TC2 10 0 9 8 7 6 0 5 4 3 2 23 22 21 20 19 18 0x8000030C 17 16 1 0 0 TC3 TC5 TC1 TC4 TC0 *) if a bit is set to 1, and the corresponding bit of GSEL_A is 0, GPIO pin is used by the other dedicated function blocks. TC5 ~ TC0 0 1 GPIO_A[11,8,7,4,3,0] Function Select GPIO_A[11,8,7,4,3,0] pin is working as Normal GPIO Function GPIO_A[11,8,7,4,3,0] is the output of 6 timer/counter *) this bit field is only valid only if the corresponding bit of GSEL_A is set to 0 GPIO_B Data Register (GDATA_B) 31 0 15 14 13 0 12 11 30 29 28 27 26 25 24 23 22 21 20 19 18 0 7 6 0 5 4 3 2 0x80000310 17 16 GPIO_B[29:21] 10 9 8 1 0 GPIO_B[9:7] GPIO_B[5:0] GPIO_B Direction Control Register (GIOCON_B) 31 0 15 14 13 0 12 11 30 29 28 27 26 25 24 23 22 21 20 19 18 0 7 6 0 5 4 3 2 0x80000314 17 16 GIO_B[29:21] 10 9 8 1 0 GIO_B[9:7] GIO_B[5:0] *) if a bit is set to 1, the corresponding GPIO pin is set to output mode. The GPIO_B[29:28] and GPIO_B[27:26] pin is unable to be set to different I/O mode. That is, GPIO_B[29] have always same direction with GPIO_B[28], and it is same as GPIO_B[27] and GPIO_B[26], so to make GPIO_B[27:26] output port, you must set both GIOCON_B[27] and GIOCON_B[26] to 1. GPIO_B Function Select Register (GSEL_B) 31 30 0 15 14 13 12 0 29 28 27 26 25 0 9 8 24 23 22 21 20 19 18 0 5 4 3 2 1 0 0x80000318 17 16 USB[1:0] 11 10 DAI[3:0] 7 6 0 UTX NWE CS[3:0] SCS CKE *) if a bit is set to 1, and the corresponding GPIO pin is set to output mode, the output of internal peripherals occupy the corresponding GPIO pin. 6-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 USB[1:0] [27:26] 0 3 GPIO_B[27:26] Function Select GPIO_B[27:26] pin is working as Normal GPIO Function GPIO_B[27] pin is working as USB D- Port GPIO_B[26] pin is working as USB D+ Port DAI[3:0] [24:21] 0 DAI[3] = 1 DAI[2] = 1 DAI[1] = 1 DAI[0] = 1 GPIO_B[24:21] Function Select GPIO_B[24:21] pin is working as Normal GPIO Function GPIO_B[24] pin is working as DAO signal of DAI block GPIO_B[23] pin is working as MCLK signal of DAI block GPIO_B[22] pin is working as LRCK signal of DAI block GPIO_B[21] pin is working as BCLK signal of DAI block UTX [8] 0 1 GPIO_B[8] Function Select GPIO_B[8] pin is working as Normal GPIO Function GPIO_B[8] : UART TX signal of UART block NWE [7] 0 1 GPIO_B[7] Function Select GPIO_B[7] pin is working as Normal GPIO Function GPIO_B[7] : ND_nWE (write enable for NAND flash) of memory controller CS[3:0] [5:2] 0 CS[3] = 1 CS[2] = 1 CS[1] = 1 CS[0] = 1 GPIO_B[5:2] Function Select GPIO_B[5:2] pin is working as Normal GPIO Function GPIO_B[5] : nCS3 or ND_nOE3 of memory controller GPIO_B[4] : nCS2 or ND_nOE2 of memory controller GPIO_B[3] : nCS1 or ND_nOE1 of memory controller GPIO_B[2] : nCS0 or ND_nOE0 of memory controller SCS [1] 0 1 GPIO_B[1] Function Select GPIO_B[1] pin is working as Normal GPIO Function GPIO_B[1] : SD_nCS (chip select for SDRAM) of memory controller CKE [0] 0 1 GPIO_B[0] Function Select GPIO_B[0] pin is working as Normal GPIO Function GPIO_B[0] : SD_CKE (clock enable for SDRAM) of memory controller 6-6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 GPIO_B Test Select Register (GTSEL_B) 31 30 29 28 0 15 14 13 12 11 10 9 IDE 27 26 25 24 EXT 8 7 23 22 GST[2:0] 6 5 4 3 21 20 19 18 0 2 0x8000031C 17 16 1 0 *) if a bit is set to 1, and the corresponding bit of GSEL_B is 0, GPIO pin is used by the other dedicated function blocks. EXT [24] 0 1 GPIO_B[24] Function Select GPIO_B[24] pin is working as Normal GPIO Function or I2S Data Output GPIO_B[24] pin is working as EXTCLK from Clock Controller IDE [9] 0 1 GPIO_B[9] Function Select GPIO_B[9] pin is working as Normal GPIO Function or UART Data Input GPIO_B[9] pin is working as chip select 1 for IDE GST[2:0] [23:21] 0 GST[2] = 1 GST[1] = 1 GST[0] = 1 GPIO_B[23:21] Function Select GPIO_B[23:21] pin is working as Normal GPIO Function GPIO_B[23] pin is working as FRM of 1 of 4 GSIO blocks GPIO_B[22] pin is working as SCK of 1 of 4 GSIO blocks GPIO_B[21] pin is working as SDO of 1 of 4 GSIO blocks *) this bit field is only valid only if the corresponding bit of GSEL_B is set to 0 6-7 CHAPTER 7 CLOCK GENERATOR TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 7 CLOCK GENERATOR 7.1 Functional Description In TCC720, there are a lot of peripherals for which has different operating frequency. To support an appropriate stable clock to each other peripherals, TCC720 has clock generator unit and for considering power consumption there is also power management unit that can manage several operating modes, such as initialization mode, normal operation mode, idle mode, stop mode. The simple block diagram of clock generator is as followings. PWRDN XIN PLLmode DIVCLK1 [18] WAITGEN PLL MUX 0 1 i_XIN WAIT PLLOUT i_XIN PLLOUT i_XIN PLLOUT FCLK 0 XTIN 1 0 1 2 MUX [22] PCLK source SCLKmode DCLKmode SCK GEN HCLK PCLK MUX [15:14] DCLK GEN DCLK 0 1 2 0 1 2 0 1 2 MUX [15:14] EXCLKmode EXTCLK GEN UTCLK GEN UBCLK GEN EXTCLK MUX [15:14] UTCLKmode UTCLK MUX [7:6] UBCLKmode UBCLK 0 1 2 0 1 2 MUX [7:6] TCLKmode TCLK GEN TCLK MUX [7:6] GCLKmode GCLK GEN GCLK Figure 7.1 Clock Generator Block Diagram 7-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 WAITGEN cell is for waiting until oscillation is stabilized. It blocks internal clocks until about 2^18 number of XIN transition occurs after reset is released. If frequency of XIN is 16MHz, the wait time is about 16.4 ms The DIVCLK1 are used as main clock of TCC720 and it can be either an oscillator output or PLL output clock. It is the source of system clocks (FCLK, HCLK, PCLK). The PCLK can be also driven by XTIN. The other clocks each can be driven by one of 3 clock sources XIN, PLLOUT, XTIN independently by its mode register. DCO Control DCLK is used as the master clock of DAI (Digital Audio Interface) block when it's mode is set to master mode. EXTCLK is used for external usage especially for CD application. UTCLK is used as the main clock of UART controller. These clocks are generated by 14bit DCO (Digital Controlled Oscillator) that can generate a stable and variable frequency as long as its frequency is below about one tenth of the divisor clock. For reliable operation of DAI, divisor clock frequency must be higher than about 200 MHz. But maximum frequency of ARM940T is lower than 120MHz, the division factor for FCLK must be greater than 2. The target frequency can be acquired by writing the phase value calculated by the following equation to the each PHASE register. D_PHASE = 214 * fDCLK / fDIV CV_PHASE = 214 * fCVCLK / fDIV EXT_PHASE = 214 * fEXTCLK / fDIV UT_PHASE = 214 * fUTCLK / fDIV For example, when you use 44.1KHz sampling rate and want to set DCLK as 256fs, the target frequency of DCLK is 256 * 44.1k = 11.2896 MHz, and if you set PLL to 266MHz, the D_PHASE value must be set to 696 ( ~= 214 * 11.2896 / 266). 7-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 7.2 Register Description Clock Generator Register Map (Base Address = 0x80000400) Name CKCTRL PLLMODE SCLKmode DCLKmode EXTCLKmode UTCLKmode UBCLKmode TCLKmode GCLKmode SW_nRST Address 0x00 0x04 0x08 0x0C 0x14 0x18 0x1C 0x24 0x28 0x3C Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x0003FFE 0x03806 0x082000 0x0800 0x0000 0x01BE 0x00 0x00 0x00 0x3FFF Description Clock Control Register PLL Control Register System Clock Control Register DCLK (DAI/CODEC) Control Register EXTCLK (CD/Other) Control Register UTCLK (UART) Control Register UBCLK (USB) Control Register TCLK (Timer) Control Register GCLK (GSIO) Control Register Software Reset for each peripherals Clock Control Register (CKCTRL) 31 30 29 28 27 26 25 24 23 22 21 20 0 7 - 0x80000400 19 18 17 16 Reserved 15 0 14 0 13 0 12 11 10 - PDN IDLE 9 8 6 5 4 3 - 2 1 0 XTIN PLL GCK TCK USB UART EXT CDC DAI PCK This controls various sources of clocks fed to each peripherals. If each control bit is set to 1, the corresponding clock is disabled and the peripherals use that clock are also disabled. To enable the clock, clear the control bit to 0. Power down and Idle mode bit are write-only register, and it is always 0 when read CKCTRL register. PDN [25] 1 Power Down Mode TCC720 goes to power down mode. All blocks disabled. IDLE [24] 1 Idle Mode TCC720 goes to idle mode. Only ARM is disabled. 7-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 XTIN [12] 1 Disable XTIN Clock Sub Clock Control PLL [11] 1 Disable PLL block PLL Control GCK [9] 1 Disable GSIO block GSIO Control TCK [8] 1 Disable Timer block Timer Control USB [6] 1 Disable USB block USB Control UART [5] 1 Disable UART block UART Control EXT [4] 1 EXT Clock Control Disable External Clock Output (EXCLK pin) CDC [2] 1 CODEC Control Disable internal CODEC block. If DAI is disabled, internal CODEC is also disabled. DAI [1] 1 Disable DAI block DAI Control If DAI is disabled, internal CODEC is also disabled. PCK [0] 1 PCLK Control Disable PCLK clock (Interrupt Control block, EFM, CIRC block, GSIO block, and ADC block are disabled) 7-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 PLL Control Register (PLLmode) 31 30 29 28 27 26 0 15 14 13 12 M 0x80000404 25 24 23 22 21 20 19 18 17 S 1 0 16 XTE DIV1 9 8 7 0 6 0 5 4 3 P 2 11 10 XTE [19] 0 1 XTIN mode select XTIN is disabled when power down is requested. XTIN is only controlled by XTIN bit of CKCTRL register DIV1 [18] 0 1 Use Oscillator as DIVCLK1 Divisor Clock1 Select Use PLL output as DIVCLK1 S/M/P S/M/P PLL Frequency Setting fPLL = (M + 8) * fXin / ((P + 2) * 2S ) The TCC720 has one PLL for generating of internal main clock. This internal PLL can generate the required frequency by setting internal register. The desired frequency can be acquired by the following equation. fPLL = (M + 8) * fXin / ((P + 2) * 2S ) Where, M, P, S can be set by PLLmode register. M has 8bit resolution, P has 6bit resolution, and S has 2bit resolution. PLL has standby mode for minimizing power consumption that can be controlled by PLL bit of CKCTRL register. 7-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 System Clock Control Register (SCLKmode) 31 30 29 28 0 15 HS 0x80000408 23 PS 22 XTI 6 0 5 4 21 20 19 18 17 16 27 26 25 24 P_PHASE 3 2 1 0 14 0 13 12 11 10 9 8 7 0 H_PHASE F_PHASE It generates FCLK, HCLK, PCLK for system operation. FCLK is dedicated for ARM940T processor, HCLK is used as internal AHB bus clock, and PCLK is for APB bus clock. Each clock is generated by 6bit DCO (Digital Controlled Oscillator) that can generate a stable and variable frequency as long as its frequency is below about 0.1 times of that of divisor clock. For reliable operation, keep the n power of 2 relationships with divisor clock. The target frequency can be acquired by writing the phase value calculated by the following equation to the PHASE register. PHASE = 26 * fSCLK / fDIV PS,XTI [23:22] 00 01 1x PCLK Clock Select use DIVCLK1 as a divisor clock of PCLK generator use XTIN pin as a divisor clock of PCLK generator use FCLK as a divisor clock of PCLK generator P_PHASE [21:16] n (!= 0) 0 fPCLK = fDIV * n / 2 6 PCLK Frequency Select fPCLK = fDIV or fXTIN (depends on PS, XTI bit) *) The DIVCLK1 is selected by DIV1 bit of PLLmode register. HS [15] 0 1 HCLK Clock Select use DIVCLK1 as a divisor clock of HCLK generator use FCLK as a divisor clock of HCLK generator H_PHASE [13:8] n (!= 0) 0 fHCLK = fDIV * n / 2 6 HCLK Frequency Select fPCLK = fDIV or fFCLK (depends on HS bit) F_PHASE [5:0] n (!= 0) 0 fFCLK = fDIV * n / 26 fPCLK = fDIV FCLK Frequency Select 7-6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 DCLK (DAI/CODEC) Control Register (DCLKmode) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 23 22 21 20 19 18 0x8000040C 17 16 1 0 DIVD D_PHASE[13:0] DIVD [15:14] 0 1 2, 3 DCLK Divisor Clock Select use XIN as a divisor clock of DCLK generator use PLL output as a divisor clock of DCLK generator use XTIN pin as a divisor clock of DCLK generator D_PHASE [13:0] d (!= 0) 0 fDCLK = fDIV * d / 214 fDCLK = fDIV DCLK Clock Frequency Select *) The divisor clock is selected by DIVD field of PLLmode register. DCLK is also controlled by DAI bit of CKCTRL register that can enable or disable DCLK. If this bit is set to high, DCLK is disabled and if it is low, DCLK is enabled. DCLK is for DAI and internal CODEC requires 512*fs frequency. To make DCLK of this frequency, first set the frequency of PLL (fDIV) more higher than 512*fs and set D_PHASE according to the above formulae. It is recommended to set the frequency of PLL by the n power of 2, than the duty ratio of DCLK is only dependant of that of PLL clock. 7-7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 EXTCLK Control Register (EXTCLKmode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000414 1 0 DIVXT EX_PHASE[13:0] DIVXT [15:14] 0 1 2, 3 EXTCLK Divisor Clock Select use XIN pin as a divisor clock of EXTCLK generator use PLL output as a divisor clock of EXTCLK generator use XTIN pin as a divisor clock of EXTCLK generator EX_PHASE [13:0] e (!= 0) 0 fEXTCLK = fDIV * e / 2 fEXTCLK = fDIV 14 EXTCLK Clock Frequency Select *) The divisor clock is selected by DIVXT bit of EXTCLKmode. EXTCLK is also controlled by EXT bit of CKCTRL register that can enable or disable EXTCLK. If this bit is set to high, EXTCLK is disabled and if it is low, EXTCLK is enabled. External clock is user-programmable clock that can be used various purposes, it is not used by internal peripherals, and by setting GPIO registers, GPIO_B24 pin can output this clock to user application board. Care must be taken not to use too high frequency that the GPIO_B24 pin cannot cope with this signals, or the GPIO_B24 pin show no clock signal out. 7-8 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 UTCLK (UART) Control Register (UTCLKmode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000418 1 0 DIVUT UT_PHASE[13:0] DIVUT [15:14] 0 1 2, 3 UTCLK Divisor Clock Select use XIN pin as a divisor clock of UTCLK generator use PLL output as a divisor clock of UTCLK generator use XTIN pin as a divisor clock of UTCLK generator UT_PHASE [13:0] u (!= 0) 0 fUTCLK = fDIV * u / 2 fUTCLK = fDIV 14 UTCLK Clock Frequency Select *) The divisor clock is selected by DIVUT bit of UTCLKmode. UTCLK is also controlled by UART bit of CKCTRL register that can enable or disable UTCLK. If this bit is set to high, UTCLK is disabled and if it is low, UTCLK is enabled This clock is used by UART. For reliable communication with host side, this clock has the frequency of 3.6864MHz or so. The UART clock is then divided by DL register in UART block, it is not so important to maintain the duty ratio of 50%. 7-9 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 UBCLK (USB) Control Register (UBCLKmode) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 9 8 7 0 6 0 5 4 3 2 23 22 21 20 19 18 0x8000041C 17 16 1 0 DIVUB UB_PHASE[5:0] UBCLK is used as the main clock of USB block. It is generated by a DCO that has 6bit resolution, and its frequency is set by writing the phase value calculated by the following equation to the UB_PHASE register. UB_PHASE = 26 * fUBCLK / fDIV UBCLK is also controlled by USB bit of CKCTRL register that can enable or disable UBCLK. If this bit is set to low, UBCLK is enabled and if it is high, UBCLK is disabled. DIVUB [9:8] 0 1 2, 3 UBCLK Divisor Clock Select use XIN pin as a divisor clock of UBCLK generator use PLL output as a divisor clock of UBCLK generator use XTIN pin as a divisor clock of UBCLK generator UB_PHASE [5:0] ub (!= 0) 0 fUBCLK = fDIV * ub / 2 fUBCLK = fDIV 6 UBCLK Clock Frequency Select *) The divisor clock is selected by DIVUB bit of UBCLKmode. UBCLK is also controlled by USB bit of CKCTRL register that can enable or disable UBCLK. If this bit is set to high, UBCLK is disabled and if it is low, UBCLK is enabled 7 - 10 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 TCLK (Timer) Control Register (TCLKmode) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 9 8 7 0 6 0 5 4 3 2 23 22 21 20 19 18 0x80000424 17 16 1 0 DIVT TC_PHASE[5:0] DIVT [9:8] 0 1 2, 3 TCLK Divisor Clock Select use XIN pin as a divisor clock of TCLK generator use PLL output as a divisor clock of TCLK generator use XTIN pin as a divisor clock of TCLK generator TC_PHASE [5:0] tc (!= 0) 0 fTC = fDIV * tc / 26 fTC = fDIV TCLK Clock Frequency Select *) The divisor clock is selected by DIVT field of TCLKmode. 7 - 11 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 GCLK (GSIO) Control Register (GCLKmode) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 9 8 7 0 6 0 5 4 3 2 23 22 21 20 19 18 0x80000428 17 16 1 0 DIVG GC_PHASE[5:0] DIVG [9:8] 0 1 2, 3 GCLK Divisor Clock Select use XIN pin as a divisor clock of GCLK generator use PLL output as a divisor clock of GCLK generator use XTIN pin as a divisor clock of GCLK generator GC_PHASE [5:0] gc (!= 0) 0 fGC = fDIV * gc / 26 fGC = fDIV GCLK Clock Frequency Select *) The divisor clock is selected by DIVG field of GCLKmode. 7 - 12 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 Software Reset Register (SW_nRST) 31 30 29 28 27 26 25 24 0 15 0 14 0 13 0 12 DMA 11 1 10 ETC 9 1 8 1 7 1 6 GS 5 UT 4 UB 3 GP 2 23 22 21 20 19 0x8000043C 18 17 16 1 IC 0 DAI TC DMA [12] 1 0 DMA Block Reset Control Reset for DMA is released Reset for DMA is generated ETC [10] 1 0 Miscellaneous Block Reset Control Reset for Miscellaneous Block is released Reset for Miscellaneous Block is generated *) Miscellaneous block contains ADC and CODEC control register and leading zero counter register, etc. GS [6] 1 0 GSIO Block Reset Control Reset for GSIO is released Reset for GSIO is generated UT [5] 1 0 UART/IrDA Block Reset Control Reset for UART/IrDA is released Reset for UART/IrDA is generated UB [4] 1 0 USB Block Reset Control Reset for USB is released Reset for USB is generated GP [3] 1 0 GPIO Block Reset Control Reset for GPIO is released Reset for GPIO is generated TC [2] 1 0 Timer/Counter Block Reset Control Reset for Timer/Counter is released Reset for Timer/Counter is generated 7 - 13 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CLOCK GENERATOR Preliminary Spec 0.51 IC [1] 1 0 Interrupt Controller Block Reset Control Reset for Interrupt Controller is released Reset for Interrupt Controller is generated DAI [0] 1 0 DAI/CDIF Block Reset Control Reset for DAI/CDIF is released Reset for DAI/CDIF is generated 7 - 14 CHAPTER 8 USB CONTROLLER TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 8 USB (Universal Serial Bus) CONTROLLER 8.1 Overview The TCC720 supports a fully compliant to USB 1.1 specification, full-speed (12 Mbps) functions and suspend/resume signaling. The USB controller is compatible with both OpenHCI and Intel UHCI standards. The USB function controller has an endpoint EP0 for control and two in/output endpoints EP1/EP2 for bulk data transaction. The endpoint EP0 has a single 16 byte FIFO; Max packet size is 16 bytes. And the endpoint EP1 and EP2 have a dual 128 byte FIFO, respectively; Max packet size of EP1 and EP2 is 64 bytes. There are 4 types of internal registers; IN_CSR (IN Control Status Register), OUT_CSR (OUT Control Status Register), IN_MAXP (IN Maximum Packet size Register), and OUT WRITE COUNT. Interrupt (Status) and Interrupt Enable registers are broken down into 2 banks: Endpoint Interrupts, USB Interrupts. The MAXP, ENDPOINT INTERRUPT and ENDPOINT INTERRUPT ENABLE registers are used regardless of the direction of the endpoint. associated CSR registers correspond to the direction of endpoint. The 8-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 8.2 Register Description USB Register Map (Base Address = 0x80000500) Name Address Type Reset NON INDEXED REGISTERS UBFADR UBPWR UBEIR UBIR UBEIEN UBIEN UBFRM1 UBFRM2 UBIDX 0x00 0x04 0x08 0x18 0x1C 0x2C 0x30 0x34 0x38 R/W R/W Function Address Register Power Management Register Endpoint Interrupt Register USB Interrupt Register Endpoint Interrupt Enable Register Interrupt Enable Register Frame Number 1 Register Frame Number 2 Register Index Register COMMON INDEXED REGISTER MAXP 0x40 IN Max Packet Register IN INDEXED REGISTERS INCSR1 INCSR2 0x44 0x48 IN CSR1 Register (EP0 CSR Register) IN CSR2 Register OUT INDEXED REGISTERS OCSR1 OCSR2 OFIFO1 OFIFO2 0x50 0x54 0x58 0x5C OUT CSR1 Register OUT CSR2 Register OUT FIFO Write Count 1 Register OUT FIFO Write Count 2 Register FIFO REGISTERS EP0FIFO EP1FIFO EP2FIFO 0x80 0x84 0x88 EP0 FIFO Register EP1 FIFO Register EP2 FIFO Register Description 8-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 Function Address Register (UBFADR) 15 14 13 12 11 10 9 8 7 UP 6 5 4 3 FADR 2 0X80000500 1 0 Reserved UP [7] UP = 0 UP = 1 Function Address Update Function address doesn't be updated Function address can be updated with FADR * The MCU sets this bit whenever it updates the FADR field. This bit is write only register. FADR [6:0] n Function Address Function address This register maintains the USB Device Address assigned by the host. The control program should write the value received through a SET_ADDRESS descriptor from host to this register. The address is used for the next token. The UP bit field should be set whenever the FADR field is written. The FADR field is used after the Status phase of a Control transfer, which is signaled by the clearing of the DATA_END bit in the endpoint EP0 CSR. 8-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 Power Management Register (UBPWR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000504 1 0 Reserved RST RSM SP ENSP RST [3] 1 Type R Reset Signal Indicates that 1 reset signaling is received from the host RSM [2] 1 Type R/W Resume Signal Initiates a resume signaling (10 ~ 15 ms duration) SP [1] 1 Type R Suspend Mode Indicates that the USB enters suspend mode ENSP [0] 0 1 Type R/W R/W Enable Suspend Mode Disable Suspend Mode Enable Suspend Mode This register is used for suspend, resume and reset signaling. If ENSP filed is zero, the device will not enter suspend mode. The SP bit field is set by the USB when it enters suspend mode. It is cleared when you clear the RSM bit field by writing zero or when the resume signal from host is received. The USB generates resume signaling while RSM bit is set in suspend mode. The RST bit field is set by USB when reset signal is received from the host. 8-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 Endpoint Interrupt Register (UBEIIR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000508 1 0 Reserved EP2 EP1 EP0 EP[2:0] [2:0] if bit n is 1 Type R EP Interrupt Flag Indicates that the USB EP interrupt has been generated USB Interrupt Register (UBIR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000518 1 0 Reserved RST RSM SP RST [2] 1 Type R Reset Interrupt Flag Indicates that the USB has received reset signaling RSM [1] 1 Type R Resume Interrupt Flag Indicates that the USB has received resume signaling in suspend mode SP [0] 1 Type R Suspend Interrupt Flag Indicates that the USB has received suspend signalizing Suspend signal is implicit signal that is generated if there is no activity for 3ms. The USB controller has two interrupt registers: Endpoint interrupt register and USB interrupt register. These registers act as status registers when interrupt is generated. Once interrupt generated, it is needed to read all the interrupt registers and write back to all the registers to clear the interrupt. The endpoint interrupt register UBEIR has three bit fields that correspond to the respective endpoints. 8-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 The EP0 interrupt is generated under the following conditions: 1. 2. 3. 4. 5. OUT Packet is ready. ORDY field is set in the CSR register IN Packet is ready. IRDY field is set in the CSR register SENT STALL is set SETUP END is set DATA END is cleared (End of control transfer) The EP1/E2 interrupt is generated under the following conditions: For IN endpoints 1. 2. 3. IRDY field is cleared in the CSR register FIFO is flushed SENT STALL is set For OUT endpoints 1. 2. ORDY field is set in the CSR register. SENT STALL is set The suspend interrupt is generated when the USB receives suspend signaling. The SP bit field of the UBIR is set whenever there is no activity for 3ms on the bus. This interrupt is disabled in default. The resume interrupt is generated by a USB reset in suspend mode. The USB reset interrupt is generated when USB controller receives the reset signaling from the host. 8-6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 Endpoint Interrupt Enable Register (UBEIEN) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x8000051C 1 0 Reserved EP2 EP1 EP0 USB Interrupt Enable Register (UBIEN) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x8000052C 1 0 Reserved RST RSM SP Corresponding to each interrupt register, there is an INTERRUPT ENABLE register (except resume interrupt enable). By default, the USB reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Frame Number 1 Register (UBFRM1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000530 1 0 Reserved FRM1 Frame Number 2 Register (UBFRM2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000534 1 0 Reserved FRM2 There are two registers, UBFRM1 and UBFRM2, which inform the frame number received from the host. The UBFRM1 denotes the lower byte of frame number. The UBFRM2 denotes the higher byte of frame number. Frame number = [UBFRM2[7:0] : UBFRM1[7:0]] 8-7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 USB Index Register (UBIDX) 15 14 13 12 11 10 9 8 7 6 5 4 IDX 3 2 0x80000538 1 0 Reserved This Index register is used to indicate the endpoint number while accessing the indexed registers: MAXP, INCSR1/2, OCSR1/2, OFIFO1/2. *) The following registers denoted by suffix letter of `n' are index register. Index register means that its address is shared by each end point blocks. So if you want to access the indexed registers of EP0, write 0 to the index register ahead, and for EP1 write 1 to the index register, and so on. Max Packet Register (MAXPn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000540 1 MAXP 0 Reserved MAXP[2:0] [2:0] n Type R/W Max Packet Number Max packet is 8*n 8-8 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 IN CSR1 Register (INCSR1n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - 0x80000544 1 0 Reserved CTGL STST ISST FLFF FNE IRDY CTGL [6] 1 Type W Clear Data Toggle Bit The data toggle bit is cleared STST [5] 1 0 Type R W STALL Handshake Issued Indicates that the STALL handshake is issued Clear by writing 0 ISST [4] 1 0 Type R/W R/W Issue STALL Handshake Start issuing a STALL Handshake Clear to end STALL condition FLFF [3] 1 0 Type R/W R Issue FIFO Flush IN FIFO is flushed This bit is cleared by the USB when the FIFO is flushed. The interrupt is generated when this happens. If a token is in progress, the USB waits until the transmission is complete before the FIFO is flushed. If two packets are loaded into the FIFO, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding IRDY bit for that packet is cleared. FNE [1] 0 1 Type R/W R/W IN FIFO Not Empty Indicates that no packet of data is in IN-FIFO Indicates that at least one packet of data is in IN-FIFO IRDY [0] 0 1 Type R W IN Packet Ready Indicates that the packet has been successfully sent to host After writing a packet of data into the IN-FIFO, set this bit to 1. 8-9 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 EP0 CSR Register (EP0CSR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000544 1 0 Reserved CLSE CLOR ISST CEND DEND STAL IRDY ORDY *) EP0 CSR register can access by writing "0" to UBIDX register, and use same address as INCSR1. CLSE [7] 1 Type W Clear Setup End Bit The SEND bit is cleared CLOR [6] 1 Type W Clear Output Packet Ready Bit The ORDY bit is cleared ISST [5] 1 Type R/W Issue STALL Handshake Start issuing a STALL Handshake. At the same time, it clears ORDY bit if it decodes an invalid token 0 W End the STALL condition CEND [4] 1 0 Type R R Control Setup End Indicates that the control transfer ends before DEND bit is set Indicates that the CLSE is written by "1". At the same time, the USB flushes the FIFO, and invalidates access to the FIFO. That is, when the access to the FIFO is invalidated, this bit is cleared. DEND [3] 1 Type R Data End Indicates that the one of the following conditions matched. after loading the last packet of data into the FIFO. (at the same time IRDY is set) while it clears ORDY after unloading the last packet of data. - for a zero length data phase (at the same time, it clears ORDY and sets IRDY) STAL [2] 1 Type R IN Packet Ready Indicates that a control transaction is ended due to a protocol violation 8 - 10 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 IRDY [1] 0 1 Type R W IN Packet Ready Indicates that the packet has been successfully sent to host After writing a packet of data into EP0 FIFO, set this bit to 1. ORDY [0] 0 1 Type R R OUT Packet Ready Indicates that the CLOR has been set to "1" Indicates that a valid token is written to the FIFO IN CSR2 Register (INCSR2n) 15 14 13 12 11 10 9 8 7 6 5 4 3 - 0x80000548 2 - 1 - 0 - Reserved ASET ISO MDIN ASET [6] 0 1 Auto Set User set IRDY flag when interrupt. IRDY is set automatically. ISO [5] 0 1 ISO Select Configures endpoint to Bulk mode Configures endpoint to ISO mode ( Not support ) MDIN [4] 0 1 IN/OUT Select Corresponding EPn is configured as OUT Mode Corresponding EPn is configured as IN Mode 8 - 11 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 OUT CSR1 Register (OCSR1n) 15 14 13 12 11 10 9 8 7 6 5 4 3 - 0x80000550 2 - 1 0 Reserved CTGL STST ISST FLFF FFL ORDY CTGL [7] 1 Type R Data Toggle Bit The data toggle sequence bit is reset to DATA0 STST [6] 1 Type R STALL Handshake Issued Indicates that the OUT token is ended with a STALL handshake ISST [5] 1 0 Type R/W R/W Issue STALL Handshake Start issuing a STALL Handshake End the STALL Condition FLFF [4] 1 0 Type R/W R/W Issue FIFO Flush OUT FIFO is flushed Stop flushing FIFO FFL [1] 1 Type R OUT FIFO Full Indicates that no more packets can be accepted ORDY [0] 0 1 Type R R OUT Packet Ready Indicates that once the MCU reads the FIFO for all the packet Once it has loaded a packet of data into the FIFO. OUT CSR2 Register (OCSR2n) 15 14 13 12 11 10 9 8 7 ACLR 0x80000554 6 - 5 - 4 - 3 - 2 - 1 - 0 - Reserved ACLR [7] 1 Type R/W Auto Clear Whenever the MCU reads data from the OUT FIFO, ORDY of OCSR1n will automatically be cleared by the core, without any intervention from MCU. 8 - 12 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 OUT FIFO Write Count 1 Register (OFIFO1n) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0x80000558 1 0 Reserved OUT FIFO Write Count 2 Register (OFIFO2n) 15 14 13 12 11 10 9 8 7 6 5 OFIFO1n 0x8000055C 4 3 2 1 0 Reserved OFIFO2n There are two register, OFIFO1n and OFIFO2n, which maintain the write count. OFIFO1n maintains the lower bytes, while OFIFO2n maintains the higher byte. When ORDY bit of OCSR1n is set for OUT endpoints, these registers maintain the number of bytes in the packet due to be unloaded by the MCU. EP0 FIFO Register (EP0FIFO) 15 14 13 12 11 10 9 8 7 6 5 4 3 FIFO 0x80000580 2 1 0 Reserved EP1 FIFO Register (EP1FIFO) 15 14 13 12 11 10 9 8 7 6 5 4 3 FIFO 0x80000584 2 1 0 Reserved EP2 FIFO Register (EP2FIFO) 15 14 13 12 11 10 9 8 7 6 5 4 3 FIFO 0x80000588 2 1 0 Reserved 8 - 13 CHAPTER 9 UART/IrDA CONTROLLER TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 9 UART / IrDA 9.1 Functional Description The TCC720 has 1 simple UART module that can be used in programming the system software or IrDA interfacing. The block diagram of UART is in the following figure. LSR CR APB Receiver FIFO Receiver Shift RZ code Demod RXD DL Transmit FIFO Transmit Shift RZ code Modulator TXD IR Interrupt Generator IREQ IrDACFG2 IrDACFG1 Figure 9.1 UART Block Diagram This UART is simplified version of UART16550, it provides only a simple interface (TXD, RXD) between host system and TCC720 system. In the UART, there are two FIFO blocks for transmission and receiving link. Transmission FIFO has 4 bytes depth, receiving FIFO has 8 bytes depth. UART can also be used as IrDA interfacing. There is a signal transformer between IrDA signal and UART signal. 9-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 9.2 Register Desciption UART/IrDA Register Map (Base Address = 0x80000600) Name RXD TXD DL IR CR LSR IrDACFG1 IrDACFG2 Address 0x00 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Type R W R/W R/W R/W R R/W R/W Reset 0x0000 0x000 0x000 0x0101 0x0003 0x4da1 Description Receiver Buffer Register Transmitter Holding Register Divisor Latch Register Interrupt Register UART Control Register Status Register IrDA Configuration Register 1 IrDA Configuration Register 2 9-2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 Receiver Buffer Register (RXD) 31 30 29 28 27 26 25 24 0 15 14 13 12 0 11 10 9 8 7 6 5 4 3 2 23 22 21 20 19 18 0x80000600 17 16 1 0 Received Data (when reading) Whenever FRX flag of IR register is set, or RA flag of LSR register is set, reading of this register gets the 1 byte of received data. Transmitter Holding Register (TXD) 31 30 29 28 27 26 25 24 0 15 14 13 12 0 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 0x80000600 17 16 Transmitting Data (when writing) When the transmission FIFO is not full, writing of this register fills that data to transmission FIFO. Checking TF flag of LSR register can monitor the status of a transmission FIFO. Divisor Latch Register (DL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000604 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Divisor Latch Value This is for generation of the desired baud rate clock. This register is set to 0 at reset, UART is disabled until this register is set by non-zero value. The value should be equal to (UART clock speed) / (16 * desired baud rate). The UART clock is generated by clock generator block. It is recommended that the frequency of UART clock is set to 3.6864MHz, so the desired baud rate can be acquired by writing (230400/baud rate) to DL register. 9-3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 Interrupt Register (IR) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 ERS 0x80000608 23 22 21 20 19 18 17 16 9 ETX 8 ERX 7 0 6 FRS 5 FTX 4 FRX 3 0 2 QRS 1 QTX 0 QRX ERS [10] 0 1 Receiver Line Status Interrupt disabled enabled ETX [9] 0 1 Transmitter Holding Register Empty Interrupt disabled enabled ERX [8] 0 1 Receiver Data Available Interrupt disabled enabled FRS [2] 0 1 Flag for Receiver Line Status Interrupt Interrupt has not generated Interrupt has generated, but not cleared FTX [1] 0 1 Flag for Transmitter Holding Register Empty Interrupt Interrupt has not generated Interrupt has generated, but not cleared FRX [0] 0 1 Flag for Receiver Data Available Interrupt Interrupt has not generated Interrupt has generated, but not cleared *) FLS, FTX, FRX is set or cleared regardless of each enable settings. QRS [2] 0 1 Request for Receiver Line Status Interrupt Interrupt has not generated Interrupt has generated, but not cleared 9-4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 QTX [1] 0 1 Request for Transmitter Holding Register Empty Interrupt Interrupt has not generated Interrupt has generated, but not cleared QRX [0] 0 1 Request for Receiver Data Available Interrupt Interrupt has not generated Interrupt has generated, but not cleared *) QRLS, QTHE, QRDA is only set when each enable bit is set to 1. 9-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 UART/IrDA Control Register (CR) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 9 NO 8 BK 7 TF 6 RF 5 4 3 PR 2 23 22 21 20 19 18 0x8000060C 17 16 1 ST 0 B7 FIFO NO [9] 0 1 Start Bit Width Check Check if the pulse width of start bit is more than 0.5 bit duration of baud rate Don't check the pulse width of start bit (used only for test or boot mode) BK [8] 0 1 Break Control Bit Normal operation Bit `0' is transmitted regardless of THR TF [7] 1 Reset Transmitter FIFO The transmitter FIFO is cleared RF [6] 1 Reset Receiver FIFO The receiver FIFO is cleared FIFO [5:4] n RX FIFO Level Select 0 = 1byte FIFO, 2 = 4 byte FIFO, 1 = 2 byte FIFO 3 = 7 byte FIFO *) This field controls the RDA(Receive Data Available) flag or interrupt only, that is the actual FIFO depth can't be modified and fixed to 8. If this field is set to 1, it means that the RDA flag or interrupt is influenced when the number of received data in the RX FIFO is 2. It is recommended that this field is set to 0, so right after reception of some data, the RDA flag or interrupt can be generated. PR [3:2] 0 1 2, 3 Parity Bit Select Even parity Odd parity Parity is disabled 9-6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 ST [1] 0 1 Stop Bit 1 Stop bit 2 Stop bit B7 [0] 0 1 Number of Bits per Character 8 bit 7 bit 9-7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 Line Status Register (LSR) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 10 0 9 8 7 6 5 4 TE 3 TF 2 FE 23 22 21 20 19 18 0x80000610 17 16 1 PE 0 RA TE [4] 0 1 *) Transmitter FIFO depth is fixed to 4. TF [3] 0 1 *) Transmitter FIFO depth is fixed to 4. FE [2] 0 1 Transmitter FIFO Not empty Empty Transmitter FIFO Not full Full Framing Status Correct stop bit is received The received data in the FIFO don't have valid stop bit PE [1] 0 1 Parity Status Correct parity bit is received The received data in the FIFO don't have valid parity bit RA [0] 0 1 Received FIFO Status No data has received At least 1 received data is in the FIFO 9-8 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 IrDA Configuration Register 1 (IrDACFG1) 31 30 29 28 27 26 25 24 0 15 EN 14 P1 13 POL 12 LB 11 10 9 8 0 7 6 5 4 3 2 23 22 21 20 19 18 0x80000614 17 16 1 PW 0 EN [15] 0 1 IrDA TX Enable IrDA TX is disabled, UART mode is used IrDA TX is enabled P1 [14] 0 1 Transmit Pulse Type Pulse width is proportional to selected baud speed Pulse width is proportional to UART base clock speed POL [13] 0 1 Transmit Pulse Polarity TX `0' data is converted to level high pulse TX `0' data is converted to level low pulse LB [12] 0 1 Normal operation Loopback Transmitted data is fed back to RX port. PW [3:0] n IrDA RZ Pulse Width Represents pulse width of TX `0' data. If n = 3, during 3/16 of its 1 bit period or 3 * 3686400-1 sec, the high pulse is generated 9-9 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 UART / IrDA Preliminary Spec 0.51 IrDA Configuration Register 2 (IrDACFG2) 31 30 29 28 27 26 25 24 0 15 EN 14 P1 13 POL 12 0 11 10 9 8 7 6 5 4 3 2 23 22 21 20 19 18 0x80000618 17 16 1 0 DEC MAX1 MIN1 EN [15] 0 1 IrDA RX Enable IrDA RX is disabled, UART mode is used IrDA RX is enabled P1 [14] 0 1 Receiver Pulse Type Received pulse width is proportional to selected baud speed Received pulse width is proportional to UART base clock speed POL [13] 0 1 Receive Pulse Polarity The polarity of received data is not inverted The polarity of received data is inverted DEC [11:8] n RX Data Decision Time The decision point for receiving data, its unit has 1/16 of baud rate. MAX1 [7:4] n Maximum number of "1"s The maximum number of "1"s to decide the received IrDA (RZ) signal as 0. If P1 is set to 1, MAX1 has the unit of 1/1843200 sec, or if P1 is set to 0, the unit of MAX1 has 1/16 of baud rate. MIN1 [3:0] n Minimum number of "1"s The minimum number of "1"s to decide the received IrDA (RZ) signal as 0. If P1 is set to 1, MIN1 has the unit of 1/1843200 sec, or if P1 is set to 0, the unit of MIN1 has 1/16 of baud rate. 9 - 10 CHAPTER 10 GSIO PORT TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GSIO Preliminary Spec 0.51 10 GSIO (General Purpose Serial Input/Output) PORT The TCC720 has three GSIOs for communication between the TCC720 and other devices that have serial interface. All the pins in the GSIOs are multiplexed with GPIOs. User can program what these multiplexed pins are used for. The GSIO block has 4 pins; SDI, SDO, SCK, FRM. The SDO is the serial data output pin, the SDI is the serial data input pin, the SCK is the serial clock pin and the FRM is frame pin. The base clock is generated by dividing the PCLK programming the GSIO control register GSCR. The SCK is generated from the basic clock in every data transfers. Various types of serial interface can be programmed using GSIO control field in the GSCR. There are 5 control registers for GSIOs; GSCR0, GSCR1, GSCR2, GSCR3, and GSICR. The start time of transfer can be controlled with programming the delay counter field in the GSCRn. The base counter increments at every base clock right after writing the data into the GSDRn. The serial data starts to come out when delay counter value are same to base counter value. The word size of transfer can be programmed from 1 bit to 16 bits. The frame1 and the frame2 fields specify the start and end point of transition based on base counter. The frame polarity defines whether the frame signal is low active or high active signal. The Last Clock mask filed is for special serial interface, which makes the last clock pulse masked. PCLK /2 n Divider base_clk SDI GSDI divider factor n SDO GSDO word_size Counter SCK Serial CLK Generator GSCR frame1, frame2 Frame Coparator GSFC FRM Figure 10.1 GSIO Block Diagram 10 - 1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GSIO Preliminary Spec 0.51 GSIO Register Map (Base Address = 0x80000700) Name GSDO0 GSDI0 GSCR0 GSGCR GSDO1 GSDI1 GSCR1 GSDO2 GSDI2 GSCR2 GSDO3 GSDI3 GSCR3 Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Description GSIO0 Output Data Register GSIO0 Input Data Register GSIO0 Control Register GSIO Global Control Register GSIO1 Output Data Register GSIO1 Input Data Register GSIO1 Control Register GSIO2 Output Data Register GSIO2 Input Data Register GSIO2 Control Register GSIO3 Output Data Register GSIO3 Input Data Register GSIO3 Control Register GSIOn Output Data Register (GSDO0, GSDO1, GSDO2, GSDO3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x800007x0 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 WORD[3:0] 2 1 0 Data to GSIO Output Pin WORD[3:0] [19:16] n GSIO word size GSIO data has (n+1) bit unit, n = 0 ~ 15 *) This field is valid only if WS of GSCRn register is set to 1. GSIOn Input Data Register (GSDI0, GSDI1, GSDI2, GSDI3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x800007x4 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data from GSIO Input Pin *) These registers is updated every writing to GSDO registers. 10 - 2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GSIO Preliminary Spec 0.51 GSIOn Control Register (GSCR0, GSCR1, GSCR2, GSCR3) 31 EN 15 0 30 MS 0x800007x8 20 19 18 17 CP 4 3 2 1 16 CM 0 29 28 27 26 25 WS 24 23 22 21 DIV WORD 13 12 FP 11 10 14 9 8 7 6 5 DELAY FRM1 FRM2 EN [31] 0 1 GSIO Enable GSIO Disabled GSIO Enabled MS [30] 0 1 First Bit Select LSB first MSB first WORD [29:26] n GSIO word size GSIO data has (n+1) bit unit, n = 0 ~ 15 WS [25] 0 1 Word Size Select GSIO word size is determined by WORD of GSCRn register GSIO word size is determined by BW of GSDO register DIV [24:18] n GSIO base clock speed control GSIO base clock has 1/(2n+2) of PCLK frequency, n = 0 ~ 127 CP [17] 0 1 GSIO clock polarity SDO changes at SCK falling SDO changes at SCK rising CM [16] 0 1 Last clock mask No mask. GSIO clock is generated for every SDO. GSIO clock is masked at the last SDO period. DELAY [14:13] n Initial delay for serial transmission GSIO transmission starts after n base clock has generated. 10 - 3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GSIO Preliminary Spec 0.51 FP [12] 0 1 Frame pulse polarity FRM has low active pulse FRM has high active pulse FRM1 [11:6] n Frame pulse start position Frame pulse starts after n base clock has generated FRM2 [5:0] n Frame pulse end position Frame pulse ends after n base clock has generated GSIO Global Control Register (GSGCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x8000070C 17 16 Reserved 15 G3 14 G2 13 G1 12 11 10 9 8 7 6 5 4 3 2 1 0 G0 IEN3 IEN2 IEN1 IEN0 FLG3 FLG2 FLG1 FLG0 Busy3 Busy2 Busy1 Busy0 G[3:0] [15:12] if bit n is 1 GPIO_B[23:21] Other Function Signal Select FRM, SCK, SDO output of GSIOn is come out from GPIO_B[23:21] *) If multiple bit of G[3:0] is set to 1, the output of each GSIO is orred and come out from GPIO_B[23:21] IEN[3:0] [11:8] if bit n is 1 0 GSIO Interrupt Enable GSIOn Interrupt is enabled GSIOn Interrupt is disabled FLG[3:0] [7:4] if bit n is 1 if bit n is 1 R/W R W GSIO Interrupt Flag GSIOn operation (read/write) has been completed. Clear FLG[n] field *) If an interrupt of a GSIO is enabled, GSIO interrupt is generated when the GSIO operation is completed. These FLGn can be used to distinguish which GSIO has generated the interrupt. These flags are cleared by writing "1" at the corresponding flag. Busy[3:0] [3:0] if bit n is 0 if bit n is 1 GSIO Cycle Busy Flag GSIOn transmission has finished, and can transmit another serial data. GSIOn transmission is in operation, so it cannot accept another serial data. 10 - 4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GSIO Preliminary Spec 0.51 The following figures represent some kinds of various GSIO operations. div_factor = 1 ; div4 = 2*(1+1) word_size = 7 ; 8bits = 7+1 init_delay = 2, clk_pol = 0 frame_pol = 1 frame1 = 18, frame2 = 20 last_clk_mask = 0 PCLK 0 base clk 1 2 3 4 5 6 7 8 9 10 .... 14 15 16 17 18 19 20 SDO D0 D1 D2 D3 .... D6 D7 SCK FRM clk_pol = 1 0 base clk 1 2 3 4 5 6 7 8 9 10 .... 14 15 16 17 18 19 20 SDO D0 D1 D2 D3 .... D6 D7 SCK FRM frame1 = 17, frame2 = 19 last_clk_mask = 1, clk_pol = 1 0 base clk 1 2 3 4 5 6 7 8 9 10 .... 14 15 16 17 18 19 20 SDO D0 D1 D2 D3 .... D6 D7 SCK FRM Figure 10.2 GSIO operation 10 - 5 CHAPTER 11 MISCELLANEOUS PERIPHERALS TCC720 MISCELLANEOUS PERIPHERALS Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 11 MISCELLANEOUS PERIPHERALS 11.1 ADC The TCC720 has 3-input general purpose low-power ADC for battery level detection, remote control interface, touch screen interface, etc. It is a CMOS type 8bit/10bit changeable A/D converter which combines suitable blocks for various purpose such as an analog input multiplexer, auto offset calibration comparator, 8bit/10bit changeable successive approximation register (SAR), etc. Various operating option can be set by using ADCCON register, it can convert up to 8 analog input and be operated as 10bit ADC at about 200ksps rates, as well as 8bit ADC at about 250ksps rates. It has standby mode for power consumption also. The output of ADC can be read from the ADCDATA register. ADC Control Register (ADCCON) 31 30 29 28 27 26 25 24 0 15 14 13 12 0 11 10 9 8 7 6 5 4 3 2 1 ASEL 0 23 22 21 20 19 18 0x80000A00 17 16 ADEN STB M8 ADEN [8:5] adc ADC Sample Rate Select Sample Rate = fPCLK / ((adc+1) * 16) STB [4] 1 0 ADC goes to standby mode ADC starts operating ADC Standby Select M8 [3] 1 0 Select 8bit conversion mode Select 10bit conversion mode ADC Bit Select ASEL [2:0] n ADC Input Select ADINn pin is selected as ADC input signal (n = one of 0, 2, 4) 11 - 1 TCC720 MISCELLANEOUS PERIPHERALS Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 ADC Data Register (ADCDATA) 31 30 29 28 27 26 25 24 0 15 14 13 0 12 11 10 9 8 7 6 5 4 3 2 23 22 21 20 19 18 0x80000A04 17 16 1 0 FLG ADATA ADATA [10:1] adc ADC Data When 8bit mode, lsb 2bit must be ignored. When 10bit mode, ADC data = adc FLG [0] 1 0 ADC Status Flag A/D conversion is finished, data is stable A/D conversion is on processing, data is unstable 11 - 2 TCC720 MISCELLANEOUS PERIPHERALS Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 11.2 CODEC The TCC720 has on-chip sigma delta type 16bit audio stereo CODEC for high grade digital audio en-decoder systems. It contains various blocks such as compensation filter, digital volume attenuator, de-emphasis filter, FIR filter, sinc filter, digital sigma-delta modulator, analog postfilter, anti-image filter, etc. CODEC Control Register (CDC_CTRL) 31 30 29 28 27 26 25 24 0 15 14 0 13 12 11 ZID 10 ZC 9 8 7 6 5 4 RST 3 DA 2 1 AD 0 23 22 21 20 19 18 0x80000A08 17 16 AIS EMP IIS FSEL ZID [11] 0 1 Zero Input Detection Control DAC Zero Input Detection is enabled DAC Zero Input Detection is disabled *) If the input data has the condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued 8192 cycles of LRCK (=32fs), then zero input is detected, and the analog postfilter output will be immediately forced to VREF. ZC [10] 0 1 Zero Cross Enable Control DAC Zero Cross Enable Control is disabled DAC Zero Cross Enable Control is enabled *) If DAC postfilter output data has the condition where it is cross VREF reference level, DAC programmable gain amplifier control register is up-dated. It is used to improve click and popnoise. If ZC is 0, DAC Programmable Gain Control Register is modified by CDC_GAIN register. AIS [9] 0 1 Analog Input Selection LCH_IN and RCH_IN input is processed MIC_IN input is processed EMP [8] 0 1 De-emphasis is disabled De-emphasis is enabled De-emphasis Control *) This bit is only useful when 44.1KHz mode. 11 - 3 TCC720 MISCELLANEOUS PERIPHERALS Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 IIS [7] 0 1 Data Format Select 16bit Right Justified Mode is selected 16bit IIS Mode is selected FSEL [6:5] 0, 3 1 2 Sample Frequency Select 32KHz, 44.1KHz, 48KHz mode (System clock must be 256*fs) 16KHz, 22.05KHz mode (System clock must be 512*fs) 8KHz, 11KHz mode (System clock must be 512*fs) RST [4] 0 1 ADC, DAC reset is released ADC, DAC reset is generated Reset Signal DA [3:2] 00 01 10 11 DAC Mode Selection DAC normal operation mode DAC mute OFF, DAC power down ON DAC mute ON , DAC power down OFF DAC mute ON , DAC power down ON AD [1:0] 00 01 10 11 ADC Mode Selection ADC normal operation mode ADC mute OFF, DAC power down ON ADC mute ON , DAC power down OFF ADC mute ON , DAC power down ON 11 - 4 TCC720 MISCELLANEOUS PERIPHERALS Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 CODEC Gain Control Register (CDC_GAIN) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 0 10 9 8 7 6 5 4 ADR 3 2 23 22 21 20 19 18 0x80000A0C 17 16 1 0 DATA ADR [5:4] 00 01 10 11 Gain Register Select ADC Left Channel is selected ADC Right Channel is selected DAC Left Channel is selected DAC Right Channel is selected DATA [3:0] n Gain Data When ADR field selects ADC Gain, ADC gain = 1.5 * n dB When ADR field selects DAC Gain, DAC gain = - 2.0 * n dB 11 - 5 TCC720 MISCELLANEOUS PERIPHERALS Preliminary Spec 0.51 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 11.3 ETCETERA Count Leading Zero Register (CLZ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000A10 17 16 CLZ[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLZ[15:0] When X is written to CLZ register, the number of zero counting from MSB of X can be calculated by reading CLZ register. If the value returned by reading CLZ register is Y, the number of zero counting from MSB of X is 32 - Y. USB Port Control Register (USB_CTRL) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 10 0 *) Must be remained to 0 TEST Mode Register (TSTSEL) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 10 0 *) Must be remained 0 9 8 7 6 5 4 3 2 B2 1 B1 0 AC 23 22 21 20 19 18 0x80000A18 17 16 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 0x80000A14 17 16 PSL CNT OVR SW US1 US0 11 - 6 CHAPTER 12 DMA CONTROLLER TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 12 DMA CONTROLLER 12.1 Functional Description TCC720 has a simple 1-channel DMA controller for data transfer. It can be used to transfer data from some kind of memory block to other kind of memory block. The block diagram of DMA controller is in the following figure. ST_SADR SINC SMSK AHB C_SADR C_DADR CH_CTRL ST_DADR DINC DMSK Address Calculator State Control Machine Figure 12.1 DMA Controller Block Diagram There are various kinds of transfer modes for DMA operation. The following table represents each type of transfer according to CHCTRL register. Table 12.1 Type of DMA transfer LOCK (CHCTRL[11]) 0 1 0 1 0 or 1 0 1 0 or 1 TYPE (CHCTRL[10:8]) 000 000 001 001 101 010 010 110 Description SINGLE type transfer without LOCK SINGLE type transfer with LOCK HW_ARBIT type transfer without LOCK HW_ARBIT type transfer with LOCK HW_BURST type transfer SW_ARBIT type transfer without LOCK SW_ARBIT type transfer with LOCK SW_BURST type transfer 12 - 1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 In SINGLE type transfer, 1 Hop of transfer occurs only once at every DMA requests. The 1 Hop of transfer means 1 burst read followed by 1 burst write. 1 burst means 1, 2 or 4 consecutive read or write cycles defined by CHCTRL[7:6] field. Hardware type transfer (HW_ARBIT, HW_BURST) means that the DMA transfer triggered by external or internal hardware blocks selected by CHCTRL[28:16] field. This field has same mapping with interrupt enable flag of interrupt controller, so the DMA transfer can be occurred as like as interrupt is generated. Software type transfer (SW_ARBIT, SW_BURST) means that the DMA transfer triggered by CHCTRL[0] flag (enable flag). When this flag is set to 1, the DMA transfer begins at the same time. Arbitration type transfer (HW_ARBIT, SW_ARBIT) means that at the end of every HOP transfer, the AHB bus is released from DMA channel so other master can occupy the bus when the master has requested the bus. Burst type transfer (HW_BURST, SW_BURST) means that once the DMA transfer occurs, all of transfers are executed without further DMA requests. Lock field controls the LOCK signal (refer to AHB specification), so that when the LOCK is set to 1, the corresponding transfer doesn't be bothered by other AHB masters like LCD controller, ARM etc. This field is only meaningful for non-burst type of transfers. 12 - 2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 12.2 Register Description DMA Controller Register Map (Base Address = 0x80000E00) Name ST_SADR SPARAM C_SADR ST_DADR DPARAM C_DADR HCOUNT CHCTRL CLRDRQ Address 0x00 0x04/0x08 0x0C 0x10 0x14/0x18 0x1C 0x20 0x24 0x28 Type R/W R/W R R/W R/W R R/W R/W W Reset Description Start Address of Source Block Parameter of Source Block Current Address of Source Block Start Address of Destination Block Parameter of Destination Block Current Address of Destination Block 0x00000000 Initial and Current Hop count 0x00000000 Channel Configuration Clear End of DMA flag Start Source Address Register (ST_SADR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000E00 17 16 ST_SADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST_SADR[15:0] *) This register contains the start address of source block for DMA transfer. The transfer begins reading data from this address. Start Destination Address Register (ST_DADR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000E10 17 16 ST_DADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST_DADR[15:0] *) This register contains the start address of destination block for DMA transfer. 12 - 3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 Source Block Parameter Register (SPARAM) 31 30 29 28 27 26 25 24 23 22 21 0x80000E04 / 0x80000E08 20 19 18 17 16 SMASK[23:8] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMASK[7:0] SINC[7:0] SMASK [23:8] 0 1 Source Address Mask Register non-masked masked *) Each bit field controls the corresponding bit of source address field. That is, if SMASK[23] is set to 1, the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is unchanged during DMA transfer. This function can be used to generate circular buffer address. SINC [7:0] sinc Source Address Increment Register Source address is added by amount of sinc at every write cycles. sinc is represented as 2's complement, so if SINC[7] is 1, the source address is decremented. The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected during DMA transfer. If the source or destination address reaches its maximum address space like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not from 0x80000000 or 0x30000000. 12 - 4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 Destination Block Parameter Register (DPARAM) 31 30 29 28 27 26 25 24 23 22 21 0x80000E14 / 0x80000E18 20 19 18 17 16 DMASK[23:8] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMASK[7:0] DINC[7:0] DMASK [23:8] 0 1 Destination Address Mask Register non-masked masked *) Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is set to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is unchanged during DMA transfer. This function can be used to generate circular buffer address. DINC [7:0] dinc Destination Address Increment Register Destination address is added by amount of dinc at every write cycles. dinc is represented as 2's complement, so if DINC[7] is 1, the destination address is decremented. The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected during DMA transfer. If the source or destination address reaches its maximum address space like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not from 0x80000000 or 0x30000000. 12 - 5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 Current Source Address Register (C_SADR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000E0C 17 16 C_SADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C_SADR[15:0] *) This register contains current source address of DMA transfer. Current Destination Address Register (C_DADR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000E1C 17 16 C_DADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C_DADR[15:0] *) This register contains current destination address of DMA transfer. HOP Count Register (HCOUNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0x80000E20 17 16 C_HCOUNT[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST_HCOUNT[15:0] C_HCOUNT [31:16] cn Current Hop Count Represent cn number of Hop transfer remains ST_HCOUNT [15:0] sn Start Hop Count Represent sn number of Hop transfer is transferred. *) At the beginning of transfer, the C_HCOUNT is stored by ST_HCOUNT register. And at the end of every hop transfer, this is decremented by 1 until reached to 0. 12 - 6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 Channel Control Register (CHCTRL) 31 30 0 15 CONT 0x80000E24 24 23 22 21 20 19 18 17 16 29 28 27 26 25 DMASEL[12:0] 13 PRI 14 12 11 LOCK 10 9 TYPE 8 7 6 5 4 3 2 1 REP 0 EN BSIZE WSIZE FLAG IEN DMASEL [28:16] non-zero Select Source of DMA Request Each bit field selects corresponding signal as a source for DMA request. The bit-map of this register is identical with the IEN of interrupt controller. So if you want to use EXINT0 pin as a source of DMA request, set DMASEL[0] as 1 and select HW_ARBIT or HW_BURST type transfer. If multiple bits of this register is set, all the corresponding signal can generate DMA request for this channel. Issue Locked Transfer DMA transfer begins from ST_SADR / ST_DADR address DMA transfer begins from C_SADR / C_DADR address It must be used after the former transfer has been executed, so that C_SADR and C_DADR contains meaningful values. Priority Priority 0 is equal to disable DMA transfer DMA channel is enabled only when have non-zero priority. CONT [15] 0 1 PRI [14:12] 0 non-zero LOCK [11] 0 1 Issue Locked Transfer DMA transfer executed without lock property DMA transfer executed with lock property *) Lock field controls the LOCK signal (refer to AHB specification), so that when the LOCK is set to 1, the corresponding transfer doesn't be bothered by other AHB masters like LCD controller, ARM etc. This field is only meaningful for non-burst type of transfers. TYPE [10:8] 000 001 101 010 110 Transfer Type SINGLE transfer HW_ARBIT transfer HW_BURST transfer SW_ARBIT transfer SW_BURST transfer *) Please refer to table 12.1 for detailed information of each transfer types. 12 - 7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 BSIZE [7:6] 0 1 2, 3 Burst Size 1 Hop transfer consists of 1 pair of read and write cycle. 1 Hop transfer consists of 2 pair of read and write cycle 1 Hop transfer consists of 4 pair of read and write cycle WSIZE [5:4] 0 1 2, 3 Word Size byte transfer half word transfer word transfer FLAG [3] 1 DMA Flag Represents that all hop of transfers are fulfilled IEN [2] 1 ahead. Interrupt Enable At the same time FLAG goes to 1, DMA interrupt request is generated. *) To generate IRQ or FIQ interrupt, the corresponding enable bit in the interrupt controller must be set to 1 CONT [1] 0 Continuous Transfer After all of hop transfer has executed, the DMA channel is disabled The DMA channel remains enabled, so when another DMA request has 1 occurred, the DMA channel start transfer data again with the same manner (type, address, increment, mask) as the latest transfer of that channel. *) This bit is only valid if the transfer type is hardware and non-burst type transfer. EN [0] DMA Channel Enable DMA channel is disabled or terminated. 0 Once terminated, user must make HCOUNT to 0 not to continue transfer after channel is re-enabled. DMA channel is enabled. If software type transfer is selected, this bit 1 generates DMA request directly, or if hardware type transfer is used, the interrupt request generates DMA request. 12 - 8 CHAPTER 13 MEMORY CONTROLLER TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 13 MEMORY CONTROLLER 13.1 Overview TCC720 has a memory controller for various kind of memory for digital media en-decoding system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories, and also support the IDE interface for HDD or USB2.0 device. It has configurable data bus width through the GPIO pin or each configuration register. The data bus width can be configured for each chip select separately The memory controller provide the power saving function for SDRAM (self refresh). The following figure represents the block diagram of memory control unit. SDCFG SDRAM State Machine SDRAM Signal Generator Refresh Controller AHB Remap Flag ExtMEM Signal Generator ExtMEM State Machine Signal Mixer Memory Control Signals CSCFGn Figure 13.1 Memory Controller Block Diagram The registers for memory controller block have the base address of 0xF0000000. 13 - 1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 Memory Controller Register Map (Base Address = 0xF0000000) Name SDCFG SDFSM MCFG TST CSCFG0 Address 0x00 0x04 0x08 0x0C 0x10 Type R/W R R/W W R/W Reset Description 0x4268A020 SDRAM Configuration Register 0xZZZZ_02 0x0000 0x0B405601 SDRAM FSM Status Register Miscellaneous Configuration Register Test mode register (must be remained zero) External Chip Select 0 Configuration Register (Initially set to SRAM) External Chip Select 1 Configuration CSCFG1 0x14 R/W 0x0150569A Register (Initially set to IDE) External Chip Select 2 Configuration CSCFG2 0x18 R/W 0x0060569A Register (Initially set to NAND) NAND flash Register Map (Base Address = N * 0x10000000) Name CMD LADDR BADDR IADDR DATA Address 0x00 0x04 0x08 0x0C 0x10 Type R/W W W W R/W Reset Description Command Cycle Register Linear Address Cycle Register Block Address Cycle Register Single Address Cycle Register Data Access Cycle Register *) N represents BASE field of CSCFGn registers. 13 - 2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 13.2 SDRAM Controller SDRAM controller can control from 64Mbit up to 256Mbit SDRAM. In TCC720 system, the SDRAM contains almost parts for system operation. (program, data, ESP buffer, etc is located in SDRAM). The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay can be programmed by internal register. The registers for SDRAM controller is as the followings. Refer to SDRAM cycle diagram in figure 13.2 SDRAM Configuration Register (SDCFG) 31 CL 0xF0000000 23 22 RC 30 BW 29 CW 28 27 26 25 24 21 20 19 RCD 18 17 16 SDBASE RD[2:1] 15 RD0 14 13 RP 12 11 RW 10 9 8 7 6 5 Refresh 4 3 2 1 0 *) The reset value means the following configuration. CL=2cycle, CW=8bit, BW=16bit, SDBASE=2, RC =3, RCD=2, RD=1, RP=2, RW=12bit, Refresh=0x20 CL [31] 0 1 CAS latency is 2 cycle CAS latency is 3 cycle CAS Latency (tCL) BW [30] 0 1 Bus Width Select Bus width for SDRAM is 32 bit Bus width for SDRAM is 16 bit CW [29:28] 0, 1 2 3 8 bit is used for CAS address 9 bit is used for CAS address 10 bit is used for CAS address CAS Width 13 - 3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 SDBASE [27:24] N RC [23:21] n SDRAM Base Address Indicates the MSB 4bit of SDRAM area. That is SDRAM base = 0xN0000000 Delay of Refresh to Idle (tRC) n number of HCLK cycle is used to meet the refresh to idle delay time RCD [20:18] n Delay of RAS to CAS (tRCD) (n+1) number of HCLK cycle is used to meet the RAS to CAS delay time RD [17:15] n Delay of Read to Precharge (tRD) n number of HCLK cycle is used to meet the read to precharge time RP [14:12] n Delay of Precharge to Refresh (tRP) (n+1) number of HCLK cycle is used to meet the precharge to refresh time RW [11] 0 1 RAS Width 12bit is used for RAS address bus 13bit is used for RAS address bus Refresh [10:0] n Refresh Cycle Every (n * 16 + 15) number of HCLK cycle has passed, the SDRAM refresh request is generated. If on going cycle has finished, the refresh cycle starts. Real refresh period depends on the period of HCLK. SDRAM FSM Status Register (SDFSM) 31 30 29 28 27 26 25 24 0 0xF0000004 23 22 21 20 19 18 17 16 15 14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDFSM *) Represents current status of finite state machine in the SDRAM controller. 13 - 4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 SDRAM Write Cycle (Non-sequential) SDCLK SDnCS nRAS nCAS XA nWE DQ DQM RAS Cmd DQ0 DQM0 WR Cmd DQ1 DQM1 WR Cmd Stop Cmd RAS tRCD CAS0 CAS1 tDO SDRAM Read Cycle (Row Actived) SDCLK SDnCS nRAS nCAS nWE DQ DQM RD Cmd SDRAM Precharge / Refresh Cycle SDCLK SDnCS nRAS nCAS nWE DQ Valid PreC Cmd RFR Cmd Memory controller goes to IDLE state tRD tRP tRC tCL DQ0 tCL Stop Cmd DQ2 DQ3 Figure 13.2 SDRAM Cycle Diagram 13 - 5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 13.3 Miscellaneous Configuration In this register, there is various special flag for TCC720 system. One of them is for supporting boot PROM. In initialization, the lower address space (0x00000000 ~ 0x0FFFFFFF) is mapped to internal or external boot ROM but after initialization, a kind of RAM must be mapped to these space as the system program including interrupt vector table is located in this area. To satisfy this requirement, TCC720 provide RM flag. BM flag is used to select the boot procedure between the 7 kinds of them. Refer to chapter of boot mode for details. BM flag is determined at the rising edge of the nRESET pin, and contains the state of GPIO_A[10:8] pin. BW flag is used to know the initial system bus width configuration. This flag is read-only, and contains the state of GPIO_A[5:4] pin at the rising edge of nRESET pin. So user can control the bus width by pulling up or down the GPIO_A[5:4] pin. 13 - 6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 Miscellaneous Configuration Register (MCFG) 31 30 29 28 27 26 25 24 0 0xF0000008 23 22 21 20 19 18 17 16 15 RDY 14 0 13 0 12 BW 11 10 9 BM 8 7 0 6 5 4 3 2 IM 1 GPO 0 RM JTEN SDEN SDS RDY [15] 0 1 Type R Bus Width Flag The state of READY pin is low. The state of READY pin is high. *) READY pin is used to extend the access cycle for the external memories, it controls directly the cycle of external memory access by setting the URDY bit of each configuration register or can be used as a flags by polling the state of this bit, especially it can be used as a ready signal of NAND flash. bw* [12:11] 00, 01 10 11 Type Bus Width Flag The corresponding memory is configured by 32bit data bus. R The corresponding memory is configured by 16bit data bus. The corresponding memory is configured by 8bit data bus. *) bw is calculated by xoring the BW field of MCFG register and BW field of CSCFGn register, that is bw = BW(of MCFG) ^ BW(of CSCFGn). BW(of MCFG) is determined by status of GPIO_A[5:4] at the rising edge of nRESET signal. BM [10:8] 000 001 010 011 100 101 110 111 Type Boot Mode Booting procedure begins at the external memory attached at nCS3 Booting for downloading firmware by UART port using XIN as main clock Booting for downloading firmware by UART port using XTIN as main clock Booting from NAND flash without decryption process. R Booting from NAND flash with decryption process. Booting from NOR flash with decryption process. Booting from HPI bus interface. Development mode: JTAG and SDRAM is enabled, and the base address of SDRAM is set to 0. The TCC721 is waiting for JTAG connection while toggling the GPIO_A[0] output. *) Except the case of BM == 0, the booting sequence always starts from the internal boot ROM. Refer to chapter of boot mode for more detailed information about booting procedure. 13 - 7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 JTEN [5] 0 1 Type R/W Master of Internal Memory Select JTAG port is disabled JTAG port is enabled SDEN [4] 0 1 Type R/W Master of Internal Memory Select SDRAM controller is disabled SDRAM controller is enabled SDS [3] 0 1 Type R/W SD_CLK output select SDRAM Clock is out from SD_CLK pin SD bit is out from SD_CLK pin GPO [1] 0/1 Type R/W SD_CLK output When SDS bit is high, this bit is out through SD_CLK pin IM [2] 0 Type SD_CLK output select Memory controller automatically into idle state, when there is no memory request during 4 cycle of HCLK. If memory request occur, R/W 1 memory controller can serve that request immediately. Memory controller is always active regardless of request state, unless power down or idle state begins. RM [0] 0 Type Remap Flag The area 0 (0x00000000 ~ 0x0FFFFFFF) space is mapped to internal / R/W 1 external boot ROM The area 0 space is released from boot ROM *) If external boot ROM is used, it is considered as default that it is attached to nCS3 chip select pin. In initialization, RM flag direct that the lower address space is mapped to internal or external boot PROM, as program running, the program contained in the internal or external boot ROM must set the RM flag to 1. After this flag is set to 1, the lower address space is released from boot PROM. This lower address space can be mapped to other memories including SDRAM or Flash by changing the base address of that memories. The RM flag can be restored to 0 by clearing bit [0] of 0xF0000008. The lower address space is remapped to boot ROM. Care must be taken not to illegally change the RM flag. 13 - 8 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 13.4 External Memory Controller External memory controller can control external memories such as NAND or NOR type flash memory and ROM, SRAM type memory. These memories are selected by nCS3 ~ nCS0 pins. The cycle parameter for accessing external memory can be configured by internal registers. In case of NAND flash, additional parameters for address, command, data cycles are provided. External Chip Select n Configuration Register (CSCFGn) 31 30 0 0xF0000010 + n*4 21 20 19 18 17 0 29 28 EPW 27 BW 26 25 24 23 22 16 MTYPE CSBASE URDY RDY 15 0 14 AMSK 13 12 11 10 CLADR 9 8 7 STP 6 5 4 PW 3 2 1 HLD 0 PSIZE *) The reset value means the following configuration for each chip select. Chip Select 0 : 16bit, SRAM, Base = 0x40000000, tSTP=0, tPW=1, tHLD=1 Chip Select 1 : 32bit, IDE, Base = 0x50000000, not use Ready, tSTP=2, tPW=4, tHLD=2 Chip Select 2 : 32bit, NAND, Base = 0x60000000, AMSK=1, PSIZE=1, cLADR=3, tSTP=2, tPW=4, tHLD=2 Chip Select 3 : 16bit, NOR, Base = 0x70000000, tSTP=2, tPW=4, tHLD=2 *bw [27:26] 0, 1 2 3 Bus width = 32 bit Bus width = 16 bit Bus width = 8 bit Bus Width Select *) The bw is determined by xoring the BW field of CSCFGn register with the BW field of MCFG register. MTYPE [25:24] 0 1 2 3 NAND type IDE type Type of External Memory SMEM_0 type (Byte write is not permitted. Ex : ROM, NOR flash) SMEM_1 type (Byte write is permitted. Ex : SRAM) CSBASE [23:20] M Chip Select n Base Address Indicates the MSB 4bit of nCS[n] area. That is nCS[n] base = M * 0x10000000 13 - 9 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 URDY [19] 1 Use Ready Ready / Busy signal monitoring is enabled The memory controller waits until the state of READY pin indicate that its access request has accomplished. RDY [18] 0 Ready / Busy Select The selected GPIO pin indicating the READY signal. The memory controller waits until this pin goes to high state. 1 The selected GPIO pin indicating the BUSY signal. The memory controller waits until this pin goes to low state. AMSK [14] 0 Address Mask Bit Upper half of data bus is masked to zero. *) In case of 16bit width NAND flash, the upper half byte must be held low, during address cycles. This bit must be set to zero. But if the system uses multiple NAND flashes by sharing a chip select but separating each data to 16 or 32bit data bus of TCC720, the AMSK must be set to 1, so the address can be fed to each NAND flashes. PSIZE [13:12] psize Page size of NAND Flash The size of one page for NAND type flash. It represents byte per page calculated by the following equation. 1 Page = 256 * 2psize CLADR [11:9] N Number of Cycle for Linear Address The number of linear address command cycle for NAND type flash. (N+1) cycle is used for generating linear address command. STP [8:6] N Number of Cycle for Setup Time (tSH) N cycle is issued between the falling edge of nCS[n] and nOE / nWE. EPW,PW [5:3] N ( = 0~15 ) Number of Cycle for Pulse Width (tPW) (N+1) cycle is issued between the falling and rising edge of nOE / nWE. HLD [2:0] N Number of Cycle for Hold Time (tHLD) N cycle is issued between the rising edge of nOE / nWE and nCS[n]. 13 - 10 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 The following figure displays the element cycle diagram for external memories. SMEM_0 Type Cycle (Bus width >= Data width) nCS XA nOE nWE DQ DQR ADDR0 tPW tSH tHLD tH DQW tSH tPW tHLD ADDR1 SMEM_0 Type Cycle (Bus width < Data width) nCS XA nOE ADDR0 tPW tSH tHLD tH DQ DQRL DQRH ADDR1 tPW SMEM_1 Type Cycle (Bus width >= Data width) nCS XA nOE nWE DQM1 DQM0 DQ[15:8] DQ[7:0] DQ0 DQ1 ADDR0 tPW tSH tHLD tH tSH tPW tHLD ADDR1 Figure 13.3 Basic Timing Diagram for External Memories In case of IDE type memories, there are two chip enable signals for it. In TCC720, each enable can be controlled by offset address space. `nCS0' reflects that the offset address range of 0 ~ 0x1F is accessed, `nCS1' reflects that 0x20 ~ 0x3F is accessed. For larger address than 0x3F, if bit5 of address value means which enable signal is activated. (0 to `nCS0', 1 to `nCS1') 13 - 11 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 In case of NAND flash type memories, there are several sub-registers for accessing. The followings are these sub-registers. (M is base field of CSCFGn register) Command Cycle Register (CMD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0xM0000000 17 16 CMD3 CMD2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD1 CMD0 *) If bus width of NAND flash is more than 8bit, the CMD1 ~ 3 may be used as command register, otherwise only CMD0 is used as command register. The following values are an example commands for NAND flash of SAMSUNG. 0x00/0x01 : Page Read Command 0x50 : Spare Read Command 0x80 : Page Program Command 0x60 : Block Erase Command 0x70 : Status Read Command (status read command is generated by reading 0xM0000700 address, not 0xM0000000) *) Refer to corresponding datasheet of NAND flash chip for detailed command list. Linear Address Cycle Register (LADDR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0xM0000004 17 16 LADDR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LADDR[15:0] *) LADDR is used as the linear address for accessing NAND flash data. The number of cycle is determined by CLADR of CSCFGn register. Memory controller assumes that the byte per page is 512, so from the second cycle of address, LADDR[31:9] value is fed to NAND flash. Block Address Cycle Register (BADDR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0xM0000008 17 16 BADDR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BADDR[15:0] *) BADDR is used as the block address for accessing NAND flash data with a block unit. The number of cycle is determined by CLADR and PSIZE of CSCFGn register. 13 - 12 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 Single Address Cycle Register (IADDR) 31 30 29 28 27 26 25 24 23 22 21 20 19 0xM000000C 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved *) When CPU writes to this register, one cycle of address cycle is generated. IADDR Data Register (DATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 0xM0000010 18 17 16 DATA3 DATA2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA1 DATA0 *) DATA3~1 may be used as the value of data register, otherwise only DATA0 is used as data register. The number of data cycle is dependent on the bus width of NAND flash and the data size of access cycle. 13 - 13 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 MEMORY CONTROLLER Preliminary Spec 0.51 14.5 Internal Memories In TCC720, there is 64Kbytes of SRAM for general purposes and 4Kbytes of ROM for system initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area 0. ROM area is dedicated to area E (0xE0000000 ~ 0xEFFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when RM flag of MCFG register is cleared to 0. In case of internal ROM, the access speed is not enough to cope with that of system bus (AHB). So when the system bus clock is higher than about 40MHz, the ROM access cycle must be extended by inserting 1 wait cycle. This wait cycle is determined by writing any value to ROM area. When writing to address the bit 2 of which is 1 (such as 0xE0000004, 0xE000000C, 0xE0000014, ...) , the wait cycle is to be inserted from the next ROM access cycle. On the other hand writing to address the bit 2 of which is 0 (such as 0xE0000000, 0xE0000008, 0xE0000010, ...), the wait cycle is to be removed from the next ROM access cycle. The access time of internal SRAM is faster than that of internal ROM, so there is no need to extend access cycle for SRAM. 13 - 14 CHAPTER 14 BOOTING PROCEDURE TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14 BOOTING PROCEDURE In the TCC720, there is a internal boot ROM for system initialization process. It contains the fundamental routines for system initialization or firmware upgrading through various interface such as UART, HPI(Host Port Interface) BUS. There are 8 modes for booting procedure. It is selected by the state of GPIO_A[10:8] at nRESET going to high. The following table represents the boot mode of TCC720. Table 14.1 Booting Mode of TCC720 BM 1 2 3 Description F/W download from UART interface with XIN clock source F/W download from UART interface with XTIN clock source NAND boot with non-security NAND must be attached to chip select 2, and use only XD[7:0] 4 NAND boot with security NAND must be attached to chip select 2, and use only XD[7:0] 5 NOR boot with security NOR must be attached to chip select 3, and bus width can be configured by BW 6 HPI boot Processing for HPI bus cycle from HOST processor 7 Development mode JTAG and SDRAM is enabled, and the base address of SDRAM is set to 0. The TCC720 is waiting for JTAG connection while toggling the GPIO_A[0] output. 0 External boot External ROM must be attached to chip select 3 14 - 1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14.1 External Boot It support an external boot ROM. When external boot mode, the sequence begins from external ROM that is attached to nCS3. The bus width of external boot ROM can be determined by state of GPIO_A[5:4] at the rising edge of nRESET pin. If GPIO_A[5:4] == 0, the bus width is 16bit, if GPIO_A[5:4] == 1, it is 8bit, otherwise, it is 32bit. (Refer to the chapter of memory controller for more details) 14 - 2 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14.2 UART Boot For the flexibility and safety of code transfer, there are 2 modes in TCC720 for selecting UART clock. One is using XIN clock divided by 8, the other is using XTIN clock. This can be selected by setting GPIO_A[10:8] appropriately as described in table 14.1. Normally, the frequency of UART need to be about 3.6864MHz. But that of XIN may be variable according to the applications. To compromise the difference of clock between TCC720 and host (most case it is a desktop PC), the code is transferred by 1 bit per 1 byte transmission. That is, although the UART transmission is accomplished by 1 byte unit, TCC720 take it as 1 bit transfer, so if the received character is not 0xFF it is regarded as 0, and if 0xFF is received, it is regarded as 1. So, to receive 32bit value, a host must transmit 32 bytes with MSB first order. Figure 14.1 illustrates the transmission of one 32bit value. Host Transmit Data = 0xABCD1234 TX (Host) RX FF 00 FF 00 FF 00 FF FF .... .... .... 00 00 FF FF 00 FF 00 00 Regarded as 10101011 0xB 00110100 0x3 0x4 0xA Host Transmit Data = 0xABCD1234 Received Data is packed to 0xABCD1234 Figure 14.1 The waveform of UART transmission Because of TCC720 always regard none 0xFF data as `0', it is more robust to set the baud rate of a host UART faster than that of TCC720. The baud rate of a host UART must be as fast as that the duration of the start bit is shorter than that of TCC720 and longer than the period of UART clock (XIN/8 or XTIN). But between each transfer cycles, it is recommended to make sufficient delay times for TCC720 to receive each data correctly. The procedure of boot code transmission is like as follows. Remember each bit is transferred by 14 - 3 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 1 byte unit. (0xFF or others) i) TCC720 enables UART as 9600 baud, none parity bit, 1 stop bit, and 7 data bits. ii) It receives initial code size of 16bit. iii) Receive a code of 32bit with order of MSB first and then 1 bit even parity information. iv) If parity check is succeeded, TCC720 transfer an acknowledgement of 0xFF, or it transfers 0x00, so a host must check if the transfer is succeeded or not. v) After all of codes are transferred TCC720 branches to address 0x00000000. This procedure is illustrated in figure 14.2. Mode Setting (9600 baud, None Parity, 1 Stop bit, 7 Data bits) consist of 16 consequtive bytes transfer with MSB first order consist of 32 consequtive bytes transfer with MSB first order Parity is even, that is, if the number of ones in the received word is even, the parity bit is 0. No Receive the size of Initial Codes ( = SIZE) Receive 1 word Receive 1 bit of parity Parity OK ? Yes Send ACK (= '0xff') Write the received code to SRAM SIZE = SIZE - 4 Send NACK (= '0x00') No SIZE == 0 ? Yes Jump to SRAM (0x00000000) Figure 14.2 UART booting procedure 14 - 4 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14.3 NAND Boot There are 2 modes in TCC720 for booting from NAND flash. One is booting from NAND flash containing a pure F/W code, the other is booting from one containing an encrypted F/W code. This can be selected by setting GPIO_A[10:8] appropriately as described in table 14.1. The NAND flash is considered to be connected with nCS2, and the bus width is 8 bit regardless of bus width configuration through GPIO_A[5:4]. The supported NAND flash types are as follows. Table 14.2 Supported NAND flash types Size (bytes) 1M 2M 4M 8M 16M 32M 64M 128M 256M Size of Page (bytes) 128 256 256 512 512 512 512 512 2048 Number of Page 4K 4K 8K 8K 16K 32K 64K 128K 64K CADR* 3 3 3 3 3 3 4 4 5 Device ID 6E EA / 64 E3 / E5 E6 73 75 76 79 AA / DA At first, TCC720 checks if the second byte of each spare area is `0xC4' or not starting from the last page to first page. It considers the page of containing `0xC4' at the second byte in that spare area as the start page of containing the initialization codes, so it copies those codes from NAND to internal SRAM. The amount of codes to be transferred is the size of page - 4. The last 4 bytes mean the start number of page which containing the main F/W codes. (TCC720 considers all memories as little endian. So the byte located first means least significant byte in 32bit number, and so on.) Regardless of encryption option, this initialization codes are not encrypted, so there is no need of decryption and TCC720 directly jump to the code just copied to internal SRAM(0x00000000). At this point, the register R0 contains the number of start page that contains the main F/W codes, and R5 contains page size. If you want change these value, modify these registers 14 - 5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 before returning from the initialization code. The initialization code must be encapsulated by the entrance command of `STR LR, [SP - #4]!', and the exit command of `LDR PC, [SP], #4'. This code may contain various routines such as memory configuration or user customized booting code itself. After the initialization code finishes, and the code returns by the above exit code, the main F/W copy code begins copy from the start page contained in R0 register. TCC720 copies the size of page - 8 bytes of codes per every page to the area starting from the address of `0x00000000'. You must configure this area appropriately before returning from the initialization code. In case of encrypted F/W code, it is decrypted and then copied to as like as in non-encrypted case. The next page number is consisted of 4 bytes and located at (the size of page - 7) ~ (the size of page - 4) in current page of data to be copied. The last 4 bytes in page of data are reserved for future use. If the next page number is equal to `0xFFFFFFFF', that page is the last page containing F/W code. TCC720 copy F/W code until this number is acquired. Figure 14.3 illustrates the organization of NAND flash. 1 Page Spare area Last Page of NAND Start flag Initialization Code (Page size - 4 bytes) Start page number (= S0) S0 1st Code of F/W (Page size - 8 bytes) next page number (= S1) S1 2nd Code of F/W (Page size - 8 bytes) next page number (= S2) S2 S1 S0 C4 Sn Last Code of F/W (Page size - 8 bytes) Last page flag (= 0xFFFFFFFF) -1 1st Page of NAND Figure 14.3 The boot code structure in NAND flash Sequence of searching for 'C4' 14 - 6 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 The procedure of booting from NAND flash is displayed in figure 14.4 Device code reading & Mode Setting (Bus width = 8bit, CADR register setting) N = last page number Read 2nd byte in spare data of page N N=N-1 Data == 0xC4 ? Yes Copy (SIZE - 4) bytes from NAND to SRAM JUMP to SRAM (0x00000000) No Initialization & Customization code is executed. It may or may not return to boot ROM N = Register R0 Read (SIZE - 8) bytes from NAND Yes Encrypted ? No Decrypt data Copy (SIZE - 8) bytes to Memory (starts from 0x00000000, can be SDRAM, SRAM by setting the base register of memory controller) Read the next page number N No N == 0xFFFFFFFF ? Yes Jump to 0x00000000 Figure 14.4 NAND boot procedure 14 - 7 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14.4 NOR Boot with Security There are two modes for booting from NOR flash. One is booting from external ROM that is commonly used for various applications, and the other is booting from encrypted external ROM that can be used to hide one's code from the non-authorized user. It can be selected by setting GPIO_A[10:8] appropriately as described in table 14.1. In both cases, the NOR flash must be connected via nCS3 signal. In case of non-encrypted mode, the F/W code in external flash is directly fetched to TCC720 without any other intermediate processing, but in case of encrypted mode, the F/W code in external flash is stored in encrypted value, so boot ROM must decrypt it ahead and then copy these codes to the other random accessible memories. Figures 14.5 illustrate the allocation map of encrypted F/W code in NOR flash. 1 byte 0x00000000 0x00000004 0x00000008 Size of Initialization Code (= SA = SA3*224 + SA2*216 + SA1*28 + SA0) SA0 SB0 SA1 24 SA2 16 8 SA3 SB3 Size of F/W Code (= SB = SB3*2 + SB2*2 + SB1*2 + SB0) SB1 SB2 Initialization Code Area (SA bytes) . . . Returning from these area, the register R0 contains the start address of F/W code SA + 8 R0 Main F/W Code Area (SB bytes) Figure 14.5 Allocation of encrypted F/W code 14 - 8 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14.5 Development mode To ease the effort for starting development withTCC720, TCC720 provides development mode in booting. In this mode, JTAG interface is enabled and set cache & protection unit of TCC720 appropriately. The table 14.4 describes the region setting in this mode. Table 14.4 Region Settings in Development Mode Region # 0 1 2 3 4 5 6 7 Start 0x00000000 0x20000000 0x40000000 0x50000000 0x60000000 0x70000000 0x80000000 0x3000F000 End 0xFFFFFFFF 0x3FFFFFFF 0x4FFFFFFF 0x5FFFFFFF 0x6FFFFFFF 0x7FFFFFFF 0xFFFFFFFF 0x3000FFFF I Cache Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled D Cache Enabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Buffer Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Protection Full Access Full Access Full Access Full Access Full Access Full Access Full Access Full Access *) The region of higher number has higher priority than that of the lower regions. That is, region 7 has highest priority and region 0 has lowest priority. After region setting finishes, it goes into a infinite loop toggling GPIO_A[0]. 14 - 9 CHAPTER 15 JTAG DEBUG INTERFACE TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 JTAG DEBUG INTERFACE Preliminary Spec 0.51 15 JTAG DEBUG INTERFACE The TCC720 has the ARM940T core as main controller, and JTAG interface for developing the application programs. It can be connected with Multi-ICE of ARM or other third party's in-circuit emulator supporting for ARM940T core. With the use of in-circuit emulator, the user can easily develop the program for his or her own system. It provides hardware breakpoints, internal register monitoring, memory dump, etc. Refer to user's manual of in-circuit emulator for more detail functions of it. 15 - 1 CHAPTER 16 PACKAGE DEMENSION TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 PACKAGE DIMENSION Preliminary Spec 0.51 16 PACKAGE DEMENSION 16.1 128-Pin TQFP 16.00BSC 14.00BSC 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 ~ 7o 0.10 +0.10 -0.01 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 16.00BSC 14.00BSC TCC720 47 46 45 44 43 42 41 40 39 37 36 35 33 34 38 0.40BSC 0.18 0.05 (0.80) 0.10 1.00 0.05 0.05 Figure 16.1 Package Dimension of 128-TQFP-1414 0.60 1.20MAX 16 - 1 0.15 |
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